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openwrt-cghmn-mt300n/target/linux/starfive/patches-6.1/0115-RISC-V-Factor-out-common-code-of-__cpu_resume_enter.patch
Zoltan HERPAI 4070e2a64c starfive: add new target for StarFive JH7100/7110 SoC 
This target adds support for the StarFive JH7100 and JH7110 SoCs, based on
6.1, as well as a couple boards equipped with these.

Specifications:

SoCs:

JH7100:
 - StarFive JH7100 dual-core RISC-V (U74, RC64GC)
 - additional monitoring (S7) and control (E24) cores
 - 2Mb L2 cache

JH7110:
 - StarFive JH7110 quad-core RISC-V (U74, RV64GC)
 - additional monitoring (S7) and control (E24) cores
 - 2Mb L2 cache

Boards:

VisionFive1:
 - JH7100 @ 1GHz
 - Memory: 8Gb LPDDR4
 - 4x USB3.0
 - 1x GBit ethernet
 - AMPak 6236 wifi / bluetooth
 - audio
 - powered via USB-C

VisionFive2:
 - JH7110 @ 1.5GHz
 - Memory: 2/4/8Gb DDR4
 - 2x Gbit ethernet
 - 2x USB3.0 / 2x USB2.0
 - eMMC / SDIO
 - various multimedia input/outputs (MIPI CSI, HDMI, audio)
 - M.2 key M slot
 - PoE support
 - powered via USB-C

Installation:
Standard SD-card installation via dd-ing the generated image to
an SD-card of at least 256Mb.

Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
2024-03-10 18:21:46 +01:00

137 lines
4.7 KiB
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From f0e2b8f9bb240d7391d3eeca55534160fd385ea8 Mon Sep 17 00:00:00 2001
From: Sia Jee Heng <jeeheng.sia@starfivetech.com>
Date: Thu, 30 Mar 2023 14:43:19 +0800
Subject: [PATCH 115/122] RISC-V: Factor out common code of
__cpu_resume_enter()
The cpu_resume() function is very similar for the suspend to disk and
suspend to ram cases. Factor out the common code into suspend_restore_csrs
macro and suspend_restore_regs macro.
Signed-off-by: Sia Jee Heng <jeeheng.sia@starfivetech.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
---
arch/riscv/include/asm/assembler.h | 62 ++++++++++++++++++++++++++++++
arch/riscv/kernel/suspend_entry.S | 34 ++--------------
2 files changed, 65 insertions(+), 31 deletions(-)
create mode 100644 arch/riscv/include/asm/assembler.h
--- /dev/null
+++ b/arch/riscv/include/asm/assembler.h
@@ -0,0 +1,62 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2023 StarFive Technology Co., Ltd.
+ *
+ * Author: Jee Heng Sia <jeeheng.sia@starfivetech.com>
+ */
+
+#ifndef __ASSEMBLY__
+#error "Only include this from assembly code"
+#endif
+
+#ifndef __ASM_ASSEMBLER_H
+#define __ASM_ASSEMBLER_H
+
+#include <asm/asm.h>
+#include <asm/asm-offsets.h>
+#include <asm/csr.h>
+
+/*
+ * suspend_restore_csrs - restore CSRs
+ */
+ .macro suspend_restore_csrs
+ REG_L t0, (SUSPEND_CONTEXT_REGS + PT_EPC)(a0)
+ csrw CSR_EPC, t0
+ REG_L t0, (SUSPEND_CONTEXT_REGS + PT_STATUS)(a0)
+ csrw CSR_STATUS, t0
+ REG_L t0, (SUSPEND_CONTEXT_REGS + PT_BADADDR)(a0)
+ csrw CSR_TVAL, t0
+ REG_L t0, (SUSPEND_CONTEXT_REGS + PT_CAUSE)(a0)
+ csrw CSR_CAUSE, t0
+ .endm
+
+/*
+ * suspend_restore_regs - Restore registers (except A0 and T0-T6)
+ */
+ .macro suspend_restore_regs
+ REG_L ra, (SUSPEND_CONTEXT_REGS + PT_RA)(a0)
+ REG_L sp, (SUSPEND_CONTEXT_REGS + PT_SP)(a0)
+ REG_L gp, (SUSPEND_CONTEXT_REGS + PT_GP)(a0)
+ REG_L tp, (SUSPEND_CONTEXT_REGS + PT_TP)(a0)
+ REG_L s0, (SUSPEND_CONTEXT_REGS + PT_S0)(a0)
+ REG_L s1, (SUSPEND_CONTEXT_REGS + PT_S1)(a0)
+ REG_L a1, (SUSPEND_CONTEXT_REGS + PT_A1)(a0)
+ REG_L a2, (SUSPEND_CONTEXT_REGS + PT_A2)(a0)
+ REG_L a3, (SUSPEND_CONTEXT_REGS + PT_A3)(a0)
+ REG_L a4, (SUSPEND_CONTEXT_REGS + PT_A4)(a0)
+ REG_L a5, (SUSPEND_CONTEXT_REGS + PT_A5)(a0)
+ REG_L a6, (SUSPEND_CONTEXT_REGS + PT_A6)(a0)
+ REG_L a7, (SUSPEND_CONTEXT_REGS + PT_A7)(a0)
+ REG_L s2, (SUSPEND_CONTEXT_REGS + PT_S2)(a0)
+ REG_L s3, (SUSPEND_CONTEXT_REGS + PT_S3)(a0)
+ REG_L s4, (SUSPEND_CONTEXT_REGS + PT_S4)(a0)
+ REG_L s5, (SUSPEND_CONTEXT_REGS + PT_S5)(a0)
+ REG_L s6, (SUSPEND_CONTEXT_REGS + PT_S6)(a0)
+ REG_L s7, (SUSPEND_CONTEXT_REGS + PT_S7)(a0)
+ REG_L s8, (SUSPEND_CONTEXT_REGS + PT_S8)(a0)
+ REG_L s9, (SUSPEND_CONTEXT_REGS + PT_S9)(a0)
+ REG_L s10, (SUSPEND_CONTEXT_REGS + PT_S10)(a0)
+ REG_L s11, (SUSPEND_CONTEXT_REGS + PT_S11)(a0)
+ .endm
+
+#endif /* __ASM_ASSEMBLER_H */
--- a/arch/riscv/kernel/suspend_entry.S
+++ b/arch/riscv/kernel/suspend_entry.S
@@ -7,6 +7,7 @@
#include <linux/linkage.h>
#include <asm/asm.h>
#include <asm/asm-offsets.h>
+#include <asm/assembler.h>
#include <asm/csr.h>
#include <asm/xip_fixup.h>
@@ -83,39 +84,10 @@ ENTRY(__cpu_resume_enter)
add a0, a1, zero
/* Restore CSRs */
- REG_L t0, (SUSPEND_CONTEXT_REGS + PT_EPC)(a0)
- csrw CSR_EPC, t0
- REG_L t0, (SUSPEND_CONTEXT_REGS + PT_STATUS)(a0)
- csrw CSR_STATUS, t0
- REG_L t0, (SUSPEND_CONTEXT_REGS + PT_BADADDR)(a0)
- csrw CSR_TVAL, t0
- REG_L t0, (SUSPEND_CONTEXT_REGS + PT_CAUSE)(a0)
- csrw CSR_CAUSE, t0
+ suspend_restore_csrs
/* Restore registers (except A0 and T0-T6) */
- REG_L ra, (SUSPEND_CONTEXT_REGS + PT_RA)(a0)
- REG_L sp, (SUSPEND_CONTEXT_REGS + PT_SP)(a0)
- REG_L gp, (SUSPEND_CONTEXT_REGS + PT_GP)(a0)
- REG_L tp, (SUSPEND_CONTEXT_REGS + PT_TP)(a0)
- REG_L s0, (SUSPEND_CONTEXT_REGS + PT_S0)(a0)
- REG_L s1, (SUSPEND_CONTEXT_REGS + PT_S1)(a0)
- REG_L a1, (SUSPEND_CONTEXT_REGS + PT_A1)(a0)
- REG_L a2, (SUSPEND_CONTEXT_REGS + PT_A2)(a0)
- REG_L a3, (SUSPEND_CONTEXT_REGS + PT_A3)(a0)
- REG_L a4, (SUSPEND_CONTEXT_REGS + PT_A4)(a0)
- REG_L a5, (SUSPEND_CONTEXT_REGS + PT_A5)(a0)
- REG_L a6, (SUSPEND_CONTEXT_REGS + PT_A6)(a0)
- REG_L a7, (SUSPEND_CONTEXT_REGS + PT_A7)(a0)
- REG_L s2, (SUSPEND_CONTEXT_REGS + PT_S2)(a0)
- REG_L s3, (SUSPEND_CONTEXT_REGS + PT_S3)(a0)
- REG_L s4, (SUSPEND_CONTEXT_REGS + PT_S4)(a0)
- REG_L s5, (SUSPEND_CONTEXT_REGS + PT_S5)(a0)
- REG_L s6, (SUSPEND_CONTEXT_REGS + PT_S6)(a0)
- REG_L s7, (SUSPEND_CONTEXT_REGS + PT_S7)(a0)
- REG_L s8, (SUSPEND_CONTEXT_REGS + PT_S8)(a0)
- REG_L s9, (SUSPEND_CONTEXT_REGS + PT_S9)(a0)
- REG_L s10, (SUSPEND_CONTEXT_REGS + PT_S10)(a0)
- REG_L s11, (SUSPEND_CONTEXT_REGS + PT_S11)(a0)
+ suspend_restore_regs
/* Return zero value */
add a0, zero, zero
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