openwrt-cghmn-mt300n/target/linux/mpc85xx/files/arch/powerpc/boot/dts/ws-ap3710i.dts

// SPDX-License-Identifier: GPL-2.0-or-later or MIT

#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>

/include/ "fsl/p1020si-pre.dtsi"
/ {
	model = "Enterasys WS-AP3710i";
	compatible = "enterasys,ws-ap3710i";

	aliases {
		ethernet0 = &enet0;
		ethernet1 = &enet2;
		led-boot = &led_power_green;
		led-failsafe = &led_power_red;
		led-running = &led_power_green;
		led-upgrade = &led_power_red;
		label-mac-device = &enet0;
	};

	chosen {
		bootargs-override = "console=ttyS0,115200";
		stdout-path = &serial0;
	};

	memory {
		device_type = "memory";
	};

	leds {
		compatible = "gpio-leds";

		wifi1 {
			gpios = <&gpio0 3 GPIO_ACTIVE_HIGH>;
			label = "ws-ap3710i:green:radio1";
			linux,default-trigger = "phy0tpt";
		};

		wifi2 {
			gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>;
			label = "ws-ap3710i:green:radio2";
			linux,default-trigger = "phy1tpt";
		};

		led_power_green: power_green {
			gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>;
			label = "ws-ap3710i:green:power";
		};

		led_power_red: power_red {
			gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>;
			label = "ws-ap3710i:red:power";
		};
	};

	keys {
		compatible = "gpio-keys";

		reset {
			label = "Reset button";
			gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
			linux,code = <KEY_RESTART>;
		};
	};

	lbc: localbus@ffe05000 {
		reg = <0 0xffe05000 0 0x1000>;
		ranges = <0x0 0x0 0x0 0xee000000 0x2000000>;

		nor@0 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "cfi-flash";
			reg = <0x0 0x0 0x2000000>;
			bank-width = <2>;
			device-width = <1>;

			partitions {
				compatible = "fixed-partitions";
				#address-cells = <1>;
				#size-cells = <1>;

				partition@0 {
					compatible = "denx,uimage";
					reg = <0x0 0x1d80000>;
					label = "firmware";
				};

				partition@1d80000 {
					reg = <0x1d80000 0x80000>;
					label = "u-boot";
					read-only;
				};

				partition@1e00000 {
					reg = <0x1e00000 0x100000>;
					label = "nvram";
					read-only;
				};

				partition@1f00000 {
					reg = <0x1f00000 0x20000>;
					label = "cfg2";
					read-only;
				};

				partition@1f20000 {
					reg = <0x1f20000 0x20000>;
					label = "cfg1";
					read-only;
				};
			};
		};
	};

	soc: soc@ffe00000 {
		ranges = <0x0 0x0 0xffe00000 0x100000>;

		gpio0: gpio-controller@fc00 {
		};

		mdio@24000 {
			phy4: ethernet-phy@4 {
				reg = <0x4>;
				reset-gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
			};
		};

		enet0: ethernet@b0000 {
			phy-connection-type = "rgmii-id";
			phy-handle = <&phy4>;
		};

		enet1: ethernet@b1000 {
			status = "disabled";
		};

		enet2: ethernet@b2000 {
			status = "disabled";
		};

		usb@22000 {
			status = "disabled";
		};

		usb@23000 {
			status = "disabled";
		};
	};

	pci0: pcie@ffe09000 {
		ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
			  0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
		reg = <0 0xffe09000 0 0x1000>;

		/* Filled by U-Boot */
		bus-range = <0x00 0x01>;
		dma-ranges = <0x2000000 0x00 0xfff00000 0x00 0xffe00000
			      0x00 0x100000 0x42000000 0x00 0x00 0x00
			      0x00 0x00 0x10000000>;

		pcie@0 {
			ranges = <0x2000000 0x0 0xa0000000
				  0x2000000 0x0 0xa0000000
				  0x0 0x20000000

				  0x1000000 0x0 0x0
				  0x1000000 0x0 0x0
				  0x0 0x100000>;
		};
	};

	pci1: pcie@ffe0a000 {
		reg = <0 0xffe0a000 0 0x1000>;
		ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
			  0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;

		/* Filled by U-Boot */
		bus-range = <0x00 0x01>;
		dma-ranges = <0x2000000 0x00 0xfff00000 0x00
			      0xffe00000 0x00 0x100000 0x42000000
			      0x00 0x00 0x00 0x00 0x00 0x10000000>;

		pcie@0 {
			ranges = <0x2000000 0x0 0x80000000
				  0x2000000 0x0 0x80000000
				  0x0 0x20000000

				  0x1000000 0x0 0x0
				  0x1000000 0x0 0x0
				  0x0 0x100000>;
		};
	};

};
/include/ "fsl/p1020si-post.dtsi"

/ {
	cpus {
		PowerPC,P1020@0 {
			bus-frequency = <399999996>;
			timebase-frequency = <50000000>;
			clock-frequency = <799999992>;
			d-cache-block-size = <0x20>;
			d-cache-size = <0x8000>;
			d-cache-sets = <0x80>;
			i-cache-block-size = <0x20>;
			i-cache-size = <0x8000>;
			i-cache-sets = <0x80>;
			cpu-release-addr = <0x0 0x0ffff280>;
			status = "okay";
			enable-method = "spin-table";
		};

		PowerPC,P1020@1 {
			bus-frequency = <399999996>;
			timebase-frequency = <50000000>;
			clock-frequency = <799999992>;
			d-cache-block-size = <0x20>;
			d-cache-size = <0x8000>;
			d-cache-sets = <0x80>;
			i-cache-block-size = <0x20>;
			i-cache-size = <0x8000>;
			i-cache-sets = <0x80>;
			cpu-release-addr = <0x0 0x0ffff2a0>;
			status = "disabled";
			enable-method = "spin-table";
		};
	};

	memory {
		reg = <0x0 0x0 0x0 0x10000000>;
	};

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		cpu1-bootpage@ff00000 {
			/* Reserve upper 1 MB for second-core-bootpage */
			reg = <0x0 0xff00000 0x0 0x100000>;
		};
	};

	soc@ffe00000 {
		bus-frequency = <399999996>;

		serial@4600 {
			clock-frequency = <399999996>;
		};

		serial@4500 {
			clock-frequency = <399999996>;
		};

		pic@40000 {
			clock-frequency = <399999996>;
		};
	};

	localbus@ffe05000 {
		bus-frequency = <24999999>;
	};
};

&enet0 {
	rx-stash-idx = <0x00>;
	rx-stash-len = <0x60>;
	bd-stash;
};

&enet2 {
	rx-stash-idx = <0x00>;
	rx-stash-len = <0x60>;
	bd-stash;
};

/*
 * For the OpenWrt 22.03 release, since Linux 5.10.138 now uses
 * aliases to determine PCI domain numbers, drop aliases so as not to
 * change the sysfs path of our wireless netdevs.
 */

/ {
	aliases {
		/delete-property/ pci0;
		/delete-property/ pci1;
	};
};