e61f06c51d
All three PCIe ports are reported non working on Meraki MR42/MR52 boards
since kernel 6.1 with the issue of PCIe PHY link never coming up thus
no WLAN cards are available on the boards.
After debugging it seems that PCIe worked on 5.15 and older purely by
accident as device DTS was using /delete-property/ perst-gpios; in each
of the 3 PCIe nodes but there was no "perst-gpios" property in the SoC DTSI
as it was still using the older "perst-gpio" property so it was not getting
removed from the device DTS.
However, in kernel 6.1 commit ("ARM: dts: qcom-*: replace deprecated
perst-gpio with perst-gpios") updated all Qualcomm DTS-es to use the newer
"perst-gpios" and thus once ipq806x moved to 6.1 PCIe stopped working as
now that property was being dropped from the device DTS.
So, since the removal of PERST pins seems to have been wrong from the start
lets drop the property removal from MR42/MR52.
Fixes: #15408
Link: https://github.com/openwrt/openwrt/pull/15509
Link: https://github.com/openwrt/openwrt/pull/15512
Signed-off-by: Robert Marko <robimarko@gmail.com>
225 lines
3.3 KiB
Plaintext
225 lines
3.3 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0 OR MIT
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#include "qcom-ipq8064-v2.0-smb208.dtsi"
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/ {
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memory {
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device_type = "memory";
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linux,usable-memory = <0x41500000 0x1ea00000>;
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reg = <0x40000000 0x20000000>;
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};
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cpus {
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idle-states {
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CPU_SPC: spc {
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status = "disabled";
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};
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};
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};
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chosen {
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bootargs-append = " console=ttyMSM0,115200n8 ubi.mtd=ubi ubi.mtd=art";
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};
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};
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&qcom_pinmux {
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mdio0_pins_active: mdio0_pins_active {
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mux {
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pins = "gpio0", "gpio1";
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function = "mdio";
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drive-strength = <2>;
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bias-pull-down;
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output-low;
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};
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clk {
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pins = "gpio1";
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input-disable;
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};
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};
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phy_active: phy_active {
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phy {
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pins = "gpio6", "gpio7";
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function = "gpio";
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drive-strength = <2>;
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bias-pull-down;
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output-high;
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};
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};
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uart1_pins: uart1_pins {
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mux {
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pins = "gpio51", "gpio52";
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function = "gsbi1";
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drive-strength = <4>;
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bias-disable;
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};
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};
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};
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&gsbi1 {
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status = "okay";
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qcom,mode = <GSBI_PROT_UART_W_FC>;
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serial@12450000 {
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status = "okay";
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pinctrl-0 = <&uart1_pins>;
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pinctrl-names = "default";
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};
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};
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&pcie0 {
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status = "okay";
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bridge@0,0 {
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reg = <0x0 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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ranges;
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wifi0: wifi@1,0 {
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compatible = "qcom,ath10k";
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status = "okay";
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reg = <0x10000 0 0 0 0>;
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};
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};
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};
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&pcie1 {
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status = "okay";
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bridge@0,0 {
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reg = <0x0 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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ranges;
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wifi1: wifi@1,0 {
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compatible = "qcom,ath10k";
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status = "okay";
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reg = <0x10000 0 0 0 0>;
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};
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};
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};
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&pcie2 {
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status = "okay";
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bridge@0,0 {
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reg = <0x0 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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ranges;
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wifi2: wifi@1,0 {
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compatible = "qcom,ath10k";
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status = "okay";
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reg = <0x10000 0 0 0 0>;
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};
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};
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};
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&adm_dma {
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status = "okay";
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};
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&nand {
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status = "okay";
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nand@0 {
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compatible = "qcom,nandcs";
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reg = <0>;
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nand-ecc-strength = <4>;
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nand-bus-width = <8>;
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nand-ecc-step-size = <512>;
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nand-is-boot-medium;
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qcom,boot-partitions = <0x0 0x2140000>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "sbl1";
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reg = <0x0 0x40000>;
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read-only;
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};
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partition@40000 {
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label = "mibib";
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reg = <0x40000 0x140000>;
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read-only;
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};
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partition@180000 {
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label = "sbl2";
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reg = <0x180000 0x140000>;
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read-only;
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};
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partition@2c0000 {
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label = "sbl3";
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reg = <0x2c0000 0x280000>;
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read-only;
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};
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partition@540000 {
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label = "ddrconfig";
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reg = <0x540000 0x120000>;
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read-only;
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};
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partition@660000 {
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label = "ssd";
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reg = <0x660000 0x120000>;
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read-only;
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};
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partition@780000 {
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label = "tz";
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reg = <0x780000 0x280000>;
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read-only;
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};
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partition@a00000 {
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label = "rpm";
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reg = <0xa00000 0x280000>;
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read-only;
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};
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partition@1fc0000 {
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label = "u-boot";
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reg = <0x1fc0000 0x180000>;
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read-only;
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};
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partition@21c0000 {
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label = "bootkernel1";
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reg = <0x21c0000 0xa80000>;
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};
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partition@2c40000 {
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label = "bootkernel2";
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reg = <0x2c40000 0xa80000>;
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};
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partition@36c0000 {
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label = "ubi";
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reg = <0x36c0000 0x46c0000>;
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};
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partition@7d80000 {
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label = "art";
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reg = <0x7d80000 0x200000>;
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read-only;
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};
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};
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};
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};
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