Enable and setup multi-cpu for qca8k switch for ipq806x based devices. Rework each DTS to enable the secondary CPU port on QCA8K switch and apply the required values originally set by the OEM in the old swconfig node. In original firmware the first CPU port was always assigned to the WAN port and the secondary CPU port was assigned to the rest of the LAN port. Follow this original implementation using an init.d script. To setup the CPU port ip tools is required. Add additional default package ip-tiny to correctly setup the CPU port. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
394 lines
6.0 KiB
Plaintext
394 lines
6.0 KiB
Plaintext
#include "qcom-ipq8065-smb208.dtsi"
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#include <dt-bindings/input/input.h>
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/ {
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model = "ZyXEL NBG6817";
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compatible = "zyxel,nbg6817", "qcom,ipq8065", "qcom,ipq8064";
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memory@0 {
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reg = <0x42000000 0x1e000000>;
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device_type = "memory";
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};
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aliases {
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mdio-gpio0 = &mdio0;
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sdcc1 = &sdcc1;
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led-boot = &power;
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led-failsafe = &power;
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led-running = &power;
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led-upgrade = &power;
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};
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chosen {
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bootargs = "rootfstype=squashfs,ext4 rootwait noinitrd fstools_ignore_partname=1";
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append-rootblock = "root=/dev/mmcblk0p";
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};
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keys {
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compatible = "gpio-keys";
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pinctrl-0 = <&button_pins>;
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pinctrl-names = "default";
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wifi {
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label = "wifi";
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gpios = <&qcom_pinmux 53 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_RFKILL>;
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linux,input-type = <EV_SW>;
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debounce-interval = <60>;
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wakeup-source;
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};
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reset {
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label = "reset";
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gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_RESTART>;
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debounce-interval = <60>;
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wakeup-source;
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};
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wps {
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label = "wps";
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gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_WPS_BUTTON>;
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debounce-interval = <60>;
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wakeup-source;
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};
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};
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leds {
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compatible = "gpio-leds";
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pinctrl-0 = <&led_pins>;
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pinctrl-names = "default";
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internet {
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label = "white:internet";
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gpios = <&qcom_pinmux 64 GPIO_ACTIVE_HIGH>;
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};
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power: power {
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label = "white:power";
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gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>;
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default-state = "keep";
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};
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wifi2g {
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label = "amber:wifi2g";
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gpios = <&qcom_pinmux 33 GPIO_ACTIVE_HIGH>;
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};
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/* wifi2g amber from the manual is missing */
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wifi5g {
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label = "amber:wifi5g";
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gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>;
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};
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/* wifi5g amber from the manual is missing */
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};
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};
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&qcom_pinmux {
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button_pins: button_pins {
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mux {
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pins = "gpio53", "gpio54", "gpio65";
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function = "gpio";
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drive-strength = <2>;
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bias-pull-up;
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};
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};
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led_pins: led_pins {
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mux {
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pins = "gpio9", "gpio26", "gpio33", "gpio64";
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function = "gpio";
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drive-strength = <2>;
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bias-pull-down;
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};
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};
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mdio0_pins: mdio0-pins {
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clk {
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pins = "gpio1";
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input-disable;
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};
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};
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rgmii2_pins: rgmii2-pins {
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tx {
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pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32" ;
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input-disable;
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};
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};
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spi_pins: spi_pins {
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cs {
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pins = "gpio20";
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drive-strength = <12>;
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};
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};
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usb0_pwr_en_pins: usb0_pwr_en_pins {
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mux {
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pins = "gpio16", "gpio17";
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function = "gpio";
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drive-strength = <12>;
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};
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pwr {
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pins = "gpio17";
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bias-pull-down;
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output-high;
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};
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ovc {
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pins = "gpio16";
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bias-pull-up;
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};
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};
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usb1_pwr_en_pins: usb1_pwr_en_pins {
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mux {
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pins = "gpio14", "gpio15";
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function = "gpio";
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drive-strength = <12>;
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};
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pwr {
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pins = "gpio14";
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bias-pull-down;
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output-high;
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};
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ovc {
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pins = "gpio15";
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bias-pull-up;
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};
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};
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};
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&gsbi5 {
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qcom,mode = <GSBI_PROT_SPI>;
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status = "okay";
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spi4: spi@1a280000 {
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status = "okay";
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pinctrl-0 = <&spi_pins>;
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pinctrl-names = "default";
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cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>;
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m25p80@0 {
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compatible = "jedec,spi-nor";
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#address-cells = <1>;
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#size-cells = <1>;
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spi-max-frequency = <51200000>;
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reg = <0>;
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partitions {
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compatible = "qcom,smem-part";
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};
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};
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};
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};
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&hs_phy_0 {
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status = "okay";
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};
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&ss_phy_0 {
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status = "okay";
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};
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&usb3_0 {
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status = "okay";
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pinctrl-0 = <&usb0_pwr_en_pins>;
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pinctrl-names = "default";
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};
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&hs_phy_1 {
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status = "okay";
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};
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&ss_phy_1 {
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status = "okay";
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};
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&usb3_1 {
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status = "okay";
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pinctrl-0 = <&usb1_pwr_en_pins>;
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pinctrl-names = "default";
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};
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&pcie0 {
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status = "okay";
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reset-gpio = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>;
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pinctrl-0 = <&pcie0_pins>;
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pinctrl-names = "default";
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};
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&pcie1 {
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status = "okay";
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reset-gpio = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>;
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pinctrl-0 = <&pcie1_pins>;
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pinctrl-names = "default";
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max-link-speed = <1>;
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};
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&mdio0 {
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status = "okay";
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pinctrl-0 = <&mdio0_pins>;
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pinctrl-names = "default";
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switch@10 {
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compatible = "qca,qca8337";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x10>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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label = "cpu";
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ethernet = <&gmac1>;
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phy-mode = "rgmii";
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tx-internal-delay-ps = <1000>;
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rx-internal-delay-ps = <1000>;
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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port@1 {
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reg = <1>;
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label = "lan1";
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phy-mode = "internal";
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phy-handle = <&phy_port1>;
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};
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port@2 {
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reg = <2>;
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label = "lan2";
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phy-mode = "internal";
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phy-handle = <&phy_port2>;
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};
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port@3 {
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reg = <3>;
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label = "lan3";
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phy-mode = "internal";
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phy-handle = <&phy_port3>;
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};
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port@4 {
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reg = <4>;
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label = "lan4";
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phy-mode = "internal";
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phy-handle = <&phy_port4>;
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};
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port@5 {
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reg = <5>;
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label = "wan";
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phy-mode = "internal";
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phy-handle = <&phy_port5>;
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};
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port@6 {
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reg = <6>;
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label = "cpu";
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ethernet = <&gmac2>;
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phy-mode = "sgmii";
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qca,sgmii-enable-pll;
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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};
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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phy_port1: phy@0 {
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reg = <0>;
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};
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phy_port2: phy@1 {
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reg = <1>;
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};
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phy_port3: phy@2 {
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reg = <2>;
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};
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phy_port4: phy@3 {
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reg = <3>;
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};
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phy_port5: phy@4 {
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reg = <4>;
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};
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};
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};
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};
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&gmac1 {
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status = "okay";
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phy-mode = "rgmii";
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qcom,id = <1>;
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qcom,phy_mdio_addr = <4>;
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qcom,poll_required = <0>;
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qcom,rgmii_delay = <1>;
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qcom,phy_mii_type = <0>;
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qcom,emulation = <0>;
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qcom,irq = <255>;
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mdiobus = <&mdio0>;
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pinctrl-0 = <&rgmii2_pins>;
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pinctrl-names = "default";
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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&gmac2 {
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status = "okay";
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phy-mode = "sgmii";
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qcom,id = <2>;
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qcom,phy_mdio_addr = <0>; /* none */
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qcom,poll_required = <0>; /* no polling */
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qcom,rgmii_delay = <0>;
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qcom,phy_mii_type = <1>;
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qcom,emulation = <0>;
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qcom,irq = <258>;
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mdiobus = <&mdio0>;
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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&sdcc1 {
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status = "okay";
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};
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&adm_dma {
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status = "okay";
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};
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