fb2c6e9d4d
Removed because they are upstream: generic/backport-5.15/704-15-v5.19-net-mtk_eth_soc-move-MAC_MCR-setting-to-mac_finish.patch https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=linux-5.15.y&id=c5c0760adc260d55265c086b9efb350ea6dda38b generic/pending-5.15/735-net-mediatek-mtk_eth_soc-release-MAC_MCR_FORCE_LINK-.patch https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=linux-5.15.y&id=448cc8b5f743985f6d1d98aa4efb386fef4c3bf2 generic/pending-5.15/736-net-ethernet-mtk_eth_soc-fix-PPE-hanging-issue.patch https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=linux-5.15.y&id=9fcadd125044007351905d40c405fadc2d3bb6d6 Add new configuration symbols for tegra target. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
64 lines
1.9 KiB
Diff
64 lines
1.9 KiB
Diff
From: Lorenzo Bianconi <lorenzo@kernel.org>
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Date: Thu, 17 Nov 2022 15:29:53 +0100
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Subject: [PATCH] net: ethernet: mtk_eth_soc: fix RSTCTRL_PPE{0,1} definitions
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Fix RSTCTRL_PPE0 and RSTCTRL_PPE1 register mask definitions for
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MTK_NETSYS_V2.
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Remove duplicated definitions.
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Fixes: 160d3a9b1929 ("net: ethernet: mtk_eth_soc: introduce MTK_NETSYS_V2 support")
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Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
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Signed-off-by: David S. Miller <davem@davemloft.net>
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---
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--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
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+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
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@@ -3241,16 +3241,17 @@ static int mtk_hw_init(struct mtk_eth *e
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return 0;
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}
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- val = RSTCTRL_FE | RSTCTRL_PPE;
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if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
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regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN, 0);
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-
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- val |= RSTCTRL_ETH;
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- if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1))
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- val |= RSTCTRL_PPE1;
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+ val = RSTCTRL_PPE0_V2;
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+ } else {
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+ val = RSTCTRL_PPE0;
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}
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- ethsys_reset(eth, val);
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+ if (MTK_HAS_CAPS(eth->soc->caps, MTK_RSTCTRL_PPE1))
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+ val |= RSTCTRL_PPE1;
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+
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+ ethsys_reset(eth, RSTCTRL_ETH | RSTCTRL_FE | val);
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if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
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regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN,
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--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
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+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
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@@ -445,18 +445,14 @@
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/* ethernet reset control register */
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#define ETHSYS_RSTCTRL 0x34
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#define RSTCTRL_FE BIT(6)
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-#define RSTCTRL_PPE BIT(31)
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-#define RSTCTRL_PPE1 BIT(30)
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+#define RSTCTRL_PPE0 BIT(31)
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+#define RSTCTRL_PPE0_V2 BIT(30)
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+#define RSTCTRL_PPE1 BIT(31)
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#define RSTCTRL_ETH BIT(23)
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/* ethernet reset check idle register */
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#define ETHSYS_FE_RST_CHK_IDLE_EN 0x28
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-/* ethernet reset control register */
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-#define ETHSYS_RSTCTRL 0x34
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-#define RSTCTRL_FE BIT(6)
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-#define RSTCTRL_PPE BIT(31)
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-
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/* ethernet dma channel agent map */
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#define ETHSYS_DMA_AG_MAP 0x408
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#define ETHSYS_DMA_AG_MAP_PDMA BIT(0)
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