4e7c991af5
* Cumulative fixes and updates for MediaTek platform. [1] * Update mt7981 pinctrl driver based on upstream kernel. [2] [1] https://lore.kernel.org/u-boot/cover.1737104723.git.weijie.gao@mediatek.com/ [2] https://lore.kernel.org/u-boot/20250124033902.187796-1-weijie.gao@mediatek.com/ Signed-off-by: Shiji Yang <yangshiji66@qq.com>
63 lines
2.0 KiB
Diff
63 lines
2.0 KiB
Diff
From 140303d0308738dfb04059333c9fc25b5159a776 Mon Sep 17 00:00:00 2001
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From: Weijie Gao <weijie.gao@mediatek.com>
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Date: Fri, 17 Jan 2025 17:18:55 +0800
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Subject: [PATCH 14/15] arm: dts: mediatek: update mt7981 mmc node
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1. Fix mmc clock order of mt7981 to match the clock name
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2. Limit the max clock of SD to 50MHz to meet SD Card Spec 2.0
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3. Increase the CLK pin driving strength to 8mA
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Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
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---
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arch/arm/dts/mt7981-sd-rfb.dts | 6 ++++--
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arch/arm/dts/mt7981.dtsi | 12 ++++++------
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2 files changed, 10 insertions(+), 8 deletions(-)
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--- a/arch/arm/dts/mt7981-sd-rfb.dts
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+++ b/arch/arm/dts/mt7981-sd-rfb.dts
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@@ -118,7 +118,7 @@
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};
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conf-clk {
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pins = "SPI1_CS";
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- drive-strength = <MTK_DRIVE_6mA>;
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+ drive-strength = <MTK_DRIVE_8mA>;
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bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
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};
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conf-rst {
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@@ -140,10 +140,12 @@
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};
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&mmc0 {
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+ assigned-clock-parents = <&topckgen CLK_TOP_CB_NET2_D4>,
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+ <&topckgen CLK_TOP_CB_NET2_D2>;
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pinctrl-names = "default";
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pinctrl-0 = <&mmc0_pins_default>;
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bus-width = <4>;
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- max-frequency = <52000000>;
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+ max-frequency = <50000000>;
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cap-sd-highspeed;
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r_smpl = <0>;
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vmmc-supply = <®_3p3v>;
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--- a/arch/arm/dts/mt7981.dtsi
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+++ b/arch/arm/dts/mt7981.dtsi
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@@ -306,13 +306,13 @@
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reg = <0x11230000 0x1000>,
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<0x11C20000 0x1000>;
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interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
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- clocks = <&topckgen CLK_TOP_EMMC_400M>,
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- <&topckgen CLK_TOP_EMMC_208M>,
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+ clocks = <&topckgen CLK_TOP_EMMC_208M>,
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+ <&topckgen CLK_TOP_EMMC_400M>,
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<&infracfg CLK_INFRA_MSDC_CK>;
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- assigned-clocks = <&topckgen CLK_TOP_EMMC_400M_SEL>,
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- <&topckgen CLK_TOP_EMMC_208M_SEL>;
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- assigned-clock-parents = <&topckgen CLK_TOP_CB_NET2_D2>,
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- <&topckgen CLK_TOP_CB_M_D2>;
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+ assigned-clocks = <&topckgen CLK_TOP_EMMC_208M_SEL>,
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+ <&topckgen CLK_TOP_EMMC_400M_SEL>;
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+ assigned-clock-parents = <&topckgen CLK_TOP_CB_M_D2>,
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+ <&topckgen CLK_TOP_CB_NET2_D2>;
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clock-names = "source", "hclk", "source_cg";
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status = "disabled";
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};
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