4e7c991af5
* Cumulative fixes and updates for MediaTek platform. [1] * Update mt7981 pinctrl driver based on upstream kernel. [2] [1] https://lore.kernel.org/u-boot/cover.1737104723.git.weijie.gao@mediatek.com/ [2] https://lore.kernel.org/u-boot/20250124033902.187796-1-weijie.gao@mediatek.com/ Signed-off-by: Shiji Yang <yangshiji66@qq.com>
220 lines
5.8 KiB
Diff
220 lines
5.8 KiB
Diff
From 4064eb22e221ce93fef7f1ec3b13ac670c6b20e2 Mon Sep 17 00:00:00 2001
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From: Weijie Gao <weijie.gao@mediatek.com>
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Date: Fri, 17 Jan 2025 17:18:17 +0800
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Subject: [PATCH 10/15] arm: dts: mediatek: add pcie support for mt7988
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This patch adds PCIe support for mt7988
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Signed-off-by: Sam Shih <sam.shih@mediatek.com>
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Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
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---
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arch/arm/dts/mt7988-rfb.dts | 18 ++++
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arch/arm/dts/mt7988.dtsi | 162 ++++++++++++++++++++++++++++++++++++
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2 files changed, 180 insertions(+)
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--- a/arch/arm/dts/mt7988-rfb.dts
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+++ b/arch/arm/dts/mt7988-rfb.dts
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@@ -63,6 +63,24 @@
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};
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};
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+&pcie0 {
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+ status = "okay";
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+};
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+
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+&pcie1 {
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+ status = "okay";
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+};
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+
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+/* PCIE2 not working in u-boot */
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+&pcie2 {
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+ status = "disabled";
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+};
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+
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+/* PCIE3 not working in u-boot */
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+&pcie3 {
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+ status = "disabled";
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+};
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+
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&pinctrl {
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i2c1_pins: i2c1-pins {
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mux {
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--- a/arch/arm/dts/mt7988.dtsi
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+++ b/arch/arm/dts/mt7988.dtsi
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@@ -188,6 +188,152 @@
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status = "okay";
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};
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+ pcie2: pcie@11280000 {
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+ compatible = "mediatek,mt7988-pcie",
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+ "mediatek,mt7986-pcie",
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+ "mediatek,mt8192-pcie";
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+ device_type = "pci";
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+ #address-cells = <3>;
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+ #size-cells = <2>;
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+ reg = <0 0x11280000 0 0x2000>;
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+ reg-names = "pcie-mac";
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+ linux,pci-domain = <3>;
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+ interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
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+ bus-range = <0x00 0xff>;
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+ ranges = <0x82000000 0 0x20200000 0 0x20200000 0 0x07e00000>;
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+ clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P2>,
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+ <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P2>,
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+ <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P2>,
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+ <&infracfg CLK_INFRA_133M_PCIE_CK_P2>;
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+ clock-names = "pl_250m", "tl_26m", "peri_26m",
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+ "top_133m";
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+ phys = <&xphyu3port0 PHY_TYPE_PCIE>;
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+ phy-names = "pcie-phy";
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+
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+ status = "disabled";
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+
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+ #interrupt-cells = <1>;
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+ interrupt-map-mask = <0 0 0 0x7>;
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+ interrupt-map = <0 0 0 1 &pcie_intc2 0>,
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+ <0 0 0 2 &pcie_intc2 1>,
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+ <0 0 0 3 &pcie_intc2 2>,
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+ <0 0 0 4 &pcie_intc2 3>;
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+
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+ pcie_intc2: interrupt-controller {
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+ #address-cells = <0>;
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+ #interrupt-cells = <1>;
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+ interrupt-controller;
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+ };
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+ };
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+
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+ pcie3: pcie@11290000 {
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+ compatible = "mediatek,mt7988-pcie",
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+ "mediatek,mt7986-pcie",
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+ "mediatek,mt8192-pcie";
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+ device_type = "pci";
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+ #address-cells = <3>;
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+ #size-cells = <2>;
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+ reg = <0 0x11290000 0 0x2000>;
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+ reg-names = "pcie-mac";
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+ linux,pci-domain = <2>;
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+ interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
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+ bus-range = <0x00 0xff>;
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+ ranges = <0x82000000 0 0x28200000 0 0x28200000 0 0x07e00000>;
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+ clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P3>,
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+ <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P3>,
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+ <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P3>,
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+ <&infracfg CLK_INFRA_133M_PCIE_CK_P3>;
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+ clock-names = "pl_250m", "tl_26m", "peri_26m",
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+ "top_133m";
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+ use-dedicated-phy;
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+
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+ status = "disabled";
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+
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+ #interrupt-cells = <1>;
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+ interrupt-map-mask = <0 0 0 0x7>;
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+ interrupt-map = <0 0 0 1 &pcie_intc3 0>,
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+ <0 0 0 2 &pcie_intc3 1>,
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+ <0 0 0 3 &pcie_intc3 2>,
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+ <0 0 0 4 &pcie_intc3 3>;
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+ pcie_intc3: interrupt-controller {
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+ #address-cells = <0>;
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+ #interrupt-cells = <1>;
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+ interrupt-controller;
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+ };
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+ };
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+
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+ pcie0: pcie@11300000 {
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+ compatible = "mediatek,mt7988-pcie",
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+ "mediatek,mt7986-pcie",
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+ "mediatek,mt8192-pcie";
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+ device_type = "pci";
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+ #address-cells = <3>;
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+ #size-cells = <2>;
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+ reg = <0 0x11300000 0 0x2000>;
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+ reg-names = "pcie-mac";
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+ linux,pci-domain = <0>;
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+ interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
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+ bus-range = <0x00 0xff>;
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+ ranges = <0x82000000 0 0x30200000 0 0x30200000 0 0x07e00000>;
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+ clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P0>,
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+ <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P0>,
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+ <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P0>,
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+ <&infracfg CLK_INFRA_133M_PCIE_CK_P0>;
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+ clock-names = "pl_250m", "tl_26m", "peri_26m",
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+ "top_133m";
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+ use-dedicated-phy;
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+
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+ status = "disabled";
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+
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+ #interrupt-cells = <1>;
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+ interrupt-map-mask = <0 0 0 0x7>;
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+ interrupt-map = <0 0 0 1 &pcie_intc0 0>,
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+ <0 0 0 2 &pcie_intc0 1>,
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+ <0 0 0 3 &pcie_intc0 2>,
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+ <0 0 0 4 &pcie_intc0 3>;
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+ pcie_intc0: interrupt-controller {
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+ #address-cells = <0>;
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+ #interrupt-cells = <1>;
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+ interrupt-controller;
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+ };
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+ };
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+
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+ pcie1: pcie@11310000 {
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+ compatible = "mediatek,mt7988-pcie",
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+ "mediatek,mt7986-pcie",
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+ "mediatek,mt8192-pcie";
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+ device_type = "pci";
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+ #address-cells = <3>;
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+ #size-cells = <2>;
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+ reg = <0 0x11310000 0 0x2000>;
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+ reg-names = "pcie-mac";
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+ linux,pci-domain = <1>;
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+ interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
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+ bus-range = <0x00 0xff>;
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+ ranges = <0x82000000 0 0x38200000 0 0x38200000 0 0x07e00000>;
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+ clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P1>,
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+ <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P1>,
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+ <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P1>,
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+ <&infracfg CLK_INFRA_133M_PCIE_CK_P1>;
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+ clock-names = "pl_250m", "tl_26m", "peri_26m",
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+ "top_133m";
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+ use-dedicated-phy;
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+
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+ status = "disabled";
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+
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+ #interrupt-cells = <1>;
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+ interrupt-map-mask = <0 0 0 0x7>;
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+ interrupt-map = <0 0 0 1 &pcie_intc1 0>,
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+ <0 0 0 2 &pcie_intc1 1>,
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+ <0 0 0 3 &pcie_intc1 2>,
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+ <0 0 0 4 &pcie_intc1 3>;
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+ pcie_intc1: interrupt-controller {
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+ #address-cells = <0>;
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+ #interrupt-cells = <1>;
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+ interrupt-controller;
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+ };
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+ };
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+
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usbtphy: usb-phy@11c50000 {
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compatible = "mediatek,mt7988",
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"mediatek,generic-tphy-v2";
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@@ -214,6 +360,22 @@
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status = "okay";
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};
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};
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+
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+ xphy: xphy@11e10000 {
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+ compatible = "mediatek,mt7988", "mediatek,xsphy";
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+ #address-cells = <2>;
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+ #size-cells = <2>;
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+ ranges;
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+ status = "disabled";
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+
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+ xphyu3port0: usb-phy@11e13000 {
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+ reg = <0 0x11e13400 0 0x500>;
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+ clocks = <&dummy_clk>;
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+ clock-names = "ref";
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+ #phy-cells = <1>;
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+ status = "okay";
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+ };
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+ };
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xfi_pextp0: syscon@11f20000 {
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compatible = "mediatek,mt7988-xfi_pextp_0", "syscon";
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