4e7c991af5
* Cumulative fixes and updates for MediaTek platform. [1] * Update mt7981 pinctrl driver based on upstream kernel. [2] [1] https://lore.kernel.org/u-boot/cover.1737104723.git.weijie.gao@mediatek.com/ [2] https://lore.kernel.org/u-boot/20250124033902.187796-1-weijie.gao@mediatek.com/ Signed-off-by: Shiji Yang <yangshiji66@qq.com>
49 lines
2.2 KiB
Diff
49 lines
2.2 KiB
Diff
From b033dfb21df8ae876ec69d84bc8c5fafd7aa8ced Mon Sep 17 00:00:00 2001
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From: Weijie Gao <weijie.gao@mediatek.com>
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Date: Fri, 17 Jan 2025 17:16:38 +0800
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Subject: [PATCH 02/15] clk: mediatek: fix uninitialized fields issue in
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INFRA_MUX struct
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This patch adds missing initialization of fields in INFRA_MUX struct
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which caused uart broken after any other infra mux being enabled by
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'clk_prepare_enable'
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Signed-off-by: Sam Shih <sam.shih@mediatek.com>
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Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
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---
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drivers/clk/mediatek/clk-mt7981.c | 1 +
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drivers/clk/mediatek/clk-mt7986.c | 1 +
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drivers/clk/mediatek/clk-mt7988.c | 1 +
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3 files changed, 3 insertions(+)
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--- a/drivers/clk/mediatek/clk-mt7981.c
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+++ b/drivers/clk/mediatek/clk-mt7981.c
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@@ -359,6 +359,7 @@ static const struct mtk_parent infra_pci
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.id = _id, .mux_reg = (_reg) + 0x8, \
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.mux_set_reg = (_reg) + 0x0, .mux_clr_reg = (_reg) + 0x4, \
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.mux_shift = _shift, .mux_mask = BIT(_width) - 1, \
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+ .gate_shift = -1, .upd_shift = -1, \
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.parent_flags = _parents, .num_parents = ARRAY_SIZE(_parents), \
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.flags = CLK_MUX_SETCLR_UPD | CLK_PARENT_MIXED, \
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}
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--- a/drivers/clk/mediatek/clk-mt7986.c
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+++ b/drivers/clk/mediatek/clk-mt7986.c
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@@ -366,6 +366,7 @@ static const struct mtk_parent infra_pci
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.id = _id, .mux_reg = (_reg) + 0x8, \
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.mux_set_reg = (_reg) + 0x0, .mux_clr_reg = (_reg) + 0x4, \
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.mux_shift = _shift, .mux_mask = BIT(_width) - 1, \
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+ .gate_shift = -1, .upd_shift = -1, \
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.parent_flags = _parents, .num_parents = ARRAY_SIZE(_parents), \
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.flags = CLK_MUX_SETCLR_UPD | CLK_PARENT_MIXED, \
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}
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--- a/drivers/clk/mediatek/clk-mt7988.c
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+++ b/drivers/clk/mediatek/clk-mt7988.c
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@@ -485,6 +485,7 @@ static const int infra_pcie_gfmux_tl_ck_
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.id = _id, .mux_reg = _reg + 0x8, .mux_set_reg = _reg + 0x0, \
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.mux_clr_reg = _reg + 0x4, .mux_shift = _shift, \
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.mux_mask = BIT(_width) - 1, .parent = _parents, \
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+ .gate_shift = -1, .upd_shift = -1, \
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.num_parents = ARRAY_SIZE(_parents), \
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.flags = CLK_MUX_SETCLR_UPD | CLK_PARENT_TOPCKGEN, \
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}
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