24ade65ab5
This patch series will provide better support for Mediatek ethernet and add support for Airoha AN8855. Signed-off-by: Shiji Yang <yangshiji66@qq.com>
65 lines
2.3 KiB
Diff
65 lines
2.3 KiB
Diff
From 0d4d8e6f47ef22ea6b3041b4c0cb27b4ed4bf188 Mon Sep 17 00:00:00 2001
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From: Weijie Gao <weijie.gao@mediatek.com>
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Date: Tue, 17 Dec 2024 16:39:23 +0800
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Subject: [PATCH 03/10] net: mediatek: use correct register field for SGMII
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speed selection
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The register field for SGMII speed selection is a 2-bit field with
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value 0 for 1Gbps and 1 for 2.5Gbps (2/3 are reserved).
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So it's necessary to set both bits instead of just setting/clearing
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only the lower bit.
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Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
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---
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drivers/net/mtk_eth.c | 12 ++++++------
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drivers/net/mtk_eth.h | 3 ++-
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2 files changed, 8 insertions(+), 7 deletions(-)
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--- a/drivers/net/mtk_eth.c
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+++ b/drivers/net/mtk_eth.c
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@@ -835,8 +835,8 @@ static int mt7531_port_sgmii_init(struct
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}
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/* Set SGMII GEN2 speed(2.5G) */
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- mt753x_reg_rmw(priv, MT7531_PHYA_CTRL_SIGNAL3(port),
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- SGMSYS_SPEED_2500, SGMSYS_SPEED_2500);
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+ mt753x_reg_rmw(priv, MT7531_PHYA_CTRL_SIGNAL3(port), SGMSYS_SPEED_MASK,
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+ FIELD_PREP(SGMSYS_SPEED_MASK, SGMSYS_SPEED_2500));
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/* Disable SGMII AN */
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mt753x_reg_rmw(priv, MT7531_PCS_CONTROL_1(port),
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@@ -1281,8 +1281,7 @@ static int mtk_phy_probe(struct udevice
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static void mtk_sgmii_an_init(struct mtk_eth_priv *priv)
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{
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/* Set SGMII GEN1 speed(1G) */
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- clrsetbits_le32(priv->sgmii_base + priv->soc->ana_rgc3,
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- SGMSYS_SPEED_2500, 0);
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+ clrbits_le32(priv->sgmii_base + priv->soc->ana_rgc3, SGMSYS_SPEED_MASK);
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/* Enable SGMII AN */
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setbits_le32(priv->sgmii_base + SGMSYS_PCS_CONTROL_1,
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@@ -1305,8 +1304,9 @@ static void mtk_sgmii_an_init(struct mtk
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static void mtk_sgmii_force_init(struct mtk_eth_priv *priv)
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{
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/* Set SGMII GEN2 speed(2.5G) */
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- setbits_le32(priv->sgmii_base + priv->soc->ana_rgc3,
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- SGMSYS_SPEED_2500);
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+ clrsetbits_le32(priv->sgmii_base + priv->soc->ana_rgc3,
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+ SGMSYS_SPEED_MASK,
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+ FIELD_PREP(SGMSYS_SPEED_MASK, SGMSYS_SPEED_2500));
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/* Disable SGMII AN */
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clrsetbits_le32(priv->sgmii_base + SGMSYS_PCS_CONTROL_1,
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--- a/drivers/net/mtk_eth.h
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+++ b/drivers/net/mtk_eth.h
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@@ -108,7 +108,8 @@ enum mkt_eth_capabilities {
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#define SGMSYS_GEN2_SPEED 0x2028
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#define SGMSYS_GEN2_SPEED_V2 0x128
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-#define SGMSYS_SPEED_2500 BIT(2)
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+#define SGMSYS_SPEED_MASK GENMASK(3, 2)
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+#define SGMSYS_SPEED_2500 1
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/* USXGMII subsystem config registers */
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/* Register to control USXGMII XFI PLL digital */
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