24ade65ab5
This patch series will provide better support for Mediatek ethernet and add support for Airoha AN8855. Signed-off-by: Shiji Yang <yangshiji66@qq.com>
29 lines
1.0 KiB
Diff
29 lines
1.0 KiB
Diff
From ba365c3d23411620d86b5baf621c8f5a4000ab33 Mon Sep 17 00:00:00 2001
|
|
From: Weijie Gao <weijie.gao@mediatek.com>
|
|
Date: Tue, 17 Dec 2024 16:39:20 +0800
|
|
Subject: [PATCH 02/10] arm: dts: mt7629: fix sgmii clock selection for
|
|
ethernet
|
|
|
|
Setup correct parent of clock CLK_TOP_SGMII_REF_1_SEL to allow
|
|
sgmiisys1 work correctly.
|
|
|
|
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
|
|
---
|
|
arch/arm/dts/mt7629.dtsi | 4 +++-
|
|
1 file changed, 3 insertions(+), 1 deletion(-)
|
|
|
|
--- a/arch/arm/dts/mt7629.dtsi
|
|
+++ b/arch/arm/dts/mt7629.dtsi
|
|
@@ -314,8 +314,10 @@
|
|
"sgmii2_cdr_ref", "sgmii2_cdr_fb",
|
|
"sgmii_ck", "eth2pll";
|
|
assigned-clocks = <&topckgen CLK_TOP_ETH_SEL>,
|
|
- <&topckgen CLK_TOP_F10M_REF_SEL>;
|
|
+ <&topckgen CLK_TOP_F10M_REF_SEL>,
|
|
+ <&topckgen CLK_TOP_SGMII_REF_1_SEL>;
|
|
assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>,
|
|
+ <&topckgen CLK_TOP_SYSPLL4_D16>,
|
|
<&topckgen CLK_TOP_SGMIIPLL_D2>;
|
|
power-domains = <&scpsys MT7629_POWER_DOMAIN_ETHSYS>;
|
|
resets = <ðsys ETHSYS_FE_RST>;
|