24ade65ab5
This patch series will provide better support for Mediatek ethernet and add support for Airoha AN8855. Signed-off-by: Shiji Yang <yangshiji66@qq.com>
46 lines
1.6 KiB
Diff
46 lines
1.6 KiB
Diff
From 6e45549f4dac42748d66462e04f940ef6737289d Mon Sep 17 00:00:00 2001
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From: Weijie Gao <weijie.gao@mediatek.com>
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Date: Tue, 17 Dec 2024 16:39:16 +0800
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Subject: [PATCH 01/10] clk: mediatek: mt7629: fix parent clock of some top
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clock muxes
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According to the mt7629 programming guide, the CLK_TOP_F10M_REF_SEL
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shares the same parent selection with CLK_TOP_IRRX_SEL, while the
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present parent selection for CLK_TOP_F10M_REF_SEL is actually used
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for CLK_TOP_SGMII_REF_1_SEL.
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Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
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---
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drivers/clk/mediatek/clk-mt7629.c | 6 +++---
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1 file changed, 3 insertions(+), 3 deletions(-)
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--- a/drivers/clk/mediatek/clk-mt7629.c
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+++ b/drivers/clk/mediatek/clk-mt7629.c
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@@ -186,7 +186,7 @@ static const int pwm_parents[] = {
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CLK_TOP_UNIVPLL2_D4
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};
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-static const int f10m_ref_parents[] = {
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+static const int sgmii_ref_1_parents[] = {
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CLK_XTAL,
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CLK_TOP_SGMIIPLL_D2
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};
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@@ -369,7 +369,7 @@ static const struct mtk_composite top_mu
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/* CLK_CFG_1 */
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MUX_GATE(CLK_TOP_PWM_SEL, pwm_parents, 0x50, 0, 2, 7),
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- MUX_GATE(CLK_TOP_F10M_REF_SEL, f10m_ref_parents, 0x50, 8, 1, 15),
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+ MUX_GATE(CLK_TOP_F10M_REF_SEL, irrx_parents, 0x50, 8, 1, 15),
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MUX_GATE(CLK_TOP_NFI_INFRA_SEL, nfi_infra_parents, 0x50, 16, 4, 23),
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MUX_GATE(CLK_TOP_FLASH_SEL, flash_parents, 0x50, 24, 3, 31),
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@@ -412,7 +412,7 @@ static const struct mtk_composite top_mu
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/* CLK_CFG_8 */
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MUX_GATE(CLK_TOP_CRYPTO_SEL, crypto_parents, 0xC0, 0, 3, 7),
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- MUX_GATE(CLK_TOP_SGMII_REF_1_SEL, f10m_ref_parents, 0xC0, 8, 1, 15),
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+ MUX_GATE(CLK_TOP_SGMII_REF_1_SEL, sgmii_ref_1_parents, 0xC0, 8, 1, 15),
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MUX_GATE(CLK_TOP_10M_SEL, gpt10m_parents, 0xC0, 16, 1, 23),
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};
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