b5f32064ed
Qualcomm Atheros IPQ807x is a modern WiSoC featuring: * Quad Core ARMv8 Cortex A-53 * @ 2.2 GHz (IPQ8072A/4A/6A/8A) Codename Hawkeye * @ 1.4 GHz (IPQ8070A/1A) Codename Acorn * Dual Band simultaneaous IEEE 802.11ax * 5G: 8x8/80 or 4x4/160MHz (IPQ8074A/8A) * 5G: 4x4/80 or 2x2/160MHz (IPQ8071A/2A/6A) * 5G: 2x2/80MHz (IPQ8070A) * 2G: 4x4/40MHz (IPQ8072A/4A/6A/8A) * 2G: 2x2/40MHz (IPQ8070A/1A) * 1x PSGMII via QCA8072/5 (Max 5x 1GbE ports) * 2x SGMII/USXGMII (1/2.5/5/10 GbE) on Hawkeye * 2x SGMII/USXGMII (1/2.5/5 GbE) on Acorn * DDR3L/4 32/16 bit up to 2400MT/s * SDIO 3.0/SD card 3.0/eMMC 5.1 * Dual USB 3.0 * One PCIe Gen2.1 and one PCIe Gen3.0 port (Single lane) * Parallel NAND (ONFI)/LCD * 6x QUP BLSP SPI/I2C/UART * I2S, PCM, and TDMA * HW PWM * 1.8V configurable GPIO * Companion PMP8074 PMIC via SPMI (GPIOS, RTC etc) Note that only v2 SOC models aka the ones ending with A suffix are supported, v1 models do not comply to the final 802.11ax and have lower clocks, lack the Gen3 PCIe etc. SoC itself has two UBI32 cores for the NSS offloading system, however currently no offloading is supported. Signed-off-by: Robert Marko <robimarko@gmail.com>
107 lines
2.9 KiB
Diff
107 lines
2.9 KiB
Diff
From 85bf71b130ab0e939f53ec9cf1131d67d148bc9a Mon Sep 17 00:00:00 2001
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From: Robert Marko <robimarko@gmail.com>
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Date: Sat, 31 Dec 2022 12:45:31 +0100
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Subject: [PATCH] cpufreq: qcom-nvmem: make qcom_cpufreq_get_msm_id() return
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the SoC ID
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Currently, qcom_cpufreq_get_msm_id() does not simply return the SoC ID
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after getting it via SMEM call but instead uses an enum to encode the
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matched SMEM ID to 2 variants of MSM8996 which are then used in
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qcom_cpufreq_kryo_name_version() to set the supported version.
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This prevents qcom_cpufreq_get_msm_id() from being universal and its doing
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more than its name suggests, so lets make it just return the SoC ID
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directly which allows matching directly on the SoC ID and removes the need
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for msm8996_version enum which simplifies the driver.
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It also allows reusing the qcom_cpufreq_get_msm_id() for new SoC-s.
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Signed-off-by: Robert Marko <robimarko@gmail.com>
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---
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drivers/cpufreq/qcom-cpufreq-nvmem.c | 44 ++++++++--------------------
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1 file changed, 12 insertions(+), 32 deletions(-)
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--- a/drivers/cpufreq/qcom-cpufreq-nvmem.c
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+++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c
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@@ -32,12 +32,6 @@
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#include <dt-bindings/arm/qcom,ids.h>
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-enum _msm8996_version {
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- MSM8996_V3,
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- MSM8996_SG,
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- NUM_OF_MSM8996_VERSIONS,
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-};
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-
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struct qcom_cpufreq_drv;
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struct qcom_cpufreq_match_data {
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@@ -136,30 +130,16 @@ static void get_krait_bin_format_b(struc
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dev_dbg(cpu_dev, "PVS version: %d\n", *pvs_ver);
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}
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-static enum _msm8996_version qcom_cpufreq_get_msm_id(void)
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+static int qcom_cpufreq_get_msm_id(void)
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{
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size_t len;
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struct socinfo *info;
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- enum _msm8996_version version;
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info = qcom_smem_get(QCOM_SMEM_HOST_ANY, SMEM_HW_SW_BUILD_ID, &len);
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if (IS_ERR(info))
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- return NUM_OF_MSM8996_VERSIONS;
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-
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- switch (info->id) {
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- case QCOM_ID_MSM8996:
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- case QCOM_ID_APQ8096:
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- version = MSM8996_V3;
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- break;
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- case QCOM_ID_MSM8996SG:
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- case QCOM_ID_APQ8096SG:
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- version = MSM8996_SG;
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- break;
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- default:
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- version = NUM_OF_MSM8996_VERSIONS;
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- }
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+ return PTR_ERR(info);
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- return version;
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+ return info->id;
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}
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static int qcom_cpufreq_kryo_name_version(struct device *cpu_dev,
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@@ -168,25 +148,25 @@ static int qcom_cpufreq_kryo_name_versio
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struct qcom_cpufreq_drv *drv)
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{
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size_t len;
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+ int msm_id;
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u8 *speedbin;
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- enum _msm8996_version msm8996_version;
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*pvs_name = NULL;
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- msm8996_version = qcom_cpufreq_get_msm_id();
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- if (NUM_OF_MSM8996_VERSIONS == msm8996_version) {
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- dev_err(cpu_dev, "Not Snapdragon 820/821!");
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- return -ENODEV;
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- }
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+ msm_id = qcom_cpufreq_get_msm_id();
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+ if (msm_id < 0)
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+ return msm_id;
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speedbin = nvmem_cell_read(speedbin_nvmem, &len);
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if (IS_ERR(speedbin))
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return PTR_ERR(speedbin);
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- switch (msm8996_version) {
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- case MSM8996_V3:
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+ switch (msm_id) {
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+ case QCOM_ID_MSM8996:
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+ case QCOM_ID_APQ8096:
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drv->versions = 1 << (unsigned int)(*speedbin);
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break;
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- case MSM8996_SG:
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+ case QCOM_ID_MSM8996SG:
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+ case QCOM_ID_APQ8096SG:
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drv->versions = 1 << ((unsigned int)(*speedbin) + 4);
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break;
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default:
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