9a24040d20
With 5.15 kernel version Linksys EAX500 family devices suffered from a big regression where the Ethernet switch became silent and started to malfunction. It was discovered later that the cause was not really the kernel upgrade itself but a hackish implementation of the hw implementation of these special routers. In the original Linksys source code, GPIO 63 was handled in a special way and was reset on reboot. Normally GPIO 63 is used for pcie2 reset but in every device we support, pcie2 is actually never used as nothing is attached to it. Linksys rerouted GPIO 63 to the switch reset pin and deviates from common hw implementation. Till now it was used an hack to handle this case... It was set pcie3 as working (while actually nothing was connected), set it to output low (for assert-deassert from the pcie init code) and be done with it. The result was that the GPIO was reset for enough time in early boot and everything worked correctly. This hack implementation was born to fail from the very start and in kernel 5.15 finally problem arised. In 5.15 pcie code changed and now the GPIO reset pin is not asserted as probe won't fail if nothing is connected to the line (the old behaviour) This result in the switch hold the reset pin and the Ethernet switch dead. On top of that with 5.15 code got optimized and simply attaching the GPIO reset to the mdio wasn't enough as the switch require at least 10ms to be correctly reset. So implement finally a correct solution where: - pcie2 is correctly disabled (nothing attached, unused) - drop the wrong output-low for pcie2 reset pin - define GPIO 63 as switch reset - Add the reset-gpios to the mdio0 node - Set the reset-post-delay-us to 12ms to correctly give time the switch to reset Fixes: #10983 Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
233 lines
3.6 KiB
Plaintext
233 lines
3.6 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
|
|
|
|
#include "qcom-ipq8064-v2.0-smb208.dtsi"
|
|
|
|
#include <dt-bindings/input/input.h>
|
|
|
|
/ {
|
|
chosen {
|
|
bootargs = "console=ttyMSM0,115200n8";
|
|
/* append to bootargs adding the root deviceblock nbr from bootloader */
|
|
append-rootblock = "ubi.mtd=";
|
|
};
|
|
};
|
|
|
|
&qcom_pinmux {
|
|
/* eax500 routers reuse the pcie2 reset pin for switch reset pin */
|
|
switch_reset: switch_reset_pins {
|
|
mux {
|
|
pins = "gpio63";
|
|
function = "gpio";
|
|
drive-strength = <12>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
};
|
|
|
|
&hs_phy_0 {
|
|
status = "okay";
|
|
};
|
|
|
|
&ss_phy_0 {
|
|
status = "okay";
|
|
};
|
|
|
|
&usb3_0 {
|
|
status = "okay";
|
|
};
|
|
|
|
&hs_phy_1 {
|
|
status = "okay";
|
|
};
|
|
|
|
&ss_phy_1 {
|
|
status = "okay";
|
|
};
|
|
|
|
&usb3_1 {
|
|
status = "okay";
|
|
};
|
|
|
|
&pcie0 {
|
|
status = "okay";
|
|
|
|
max-link-speed = <1>;
|
|
};
|
|
|
|
&pcie1 {
|
|
status = "okay";
|
|
};
|
|
|
|
&nand {
|
|
status = "okay";
|
|
|
|
nand@0 {
|
|
reg = <0>;
|
|
compatible = "qcom,nandcs";
|
|
|
|
nand-ecc-strength = <4>;
|
|
nand-bus-width = <8>;
|
|
nand-ecc-step-size = <512>;
|
|
|
|
nand-is-boot-medium;
|
|
qcom,boot-partitions = <0x0 0x0c80000>;
|
|
|
|
partitions: partitions {
|
|
compatible = "fixed-partitions";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
|
|
partition@0 {
|
|
label = "SBL1";
|
|
reg = <0x0000000 0x0040000>;
|
|
read-only;
|
|
};
|
|
|
|
partition@40000 {
|
|
label = "MIBIB";
|
|
reg = <0x0040000 0x0140000>;
|
|
read-only;
|
|
};
|
|
|
|
partition@180000 {
|
|
label = "SBL2";
|
|
reg = <0x0180000 0x0140000>;
|
|
read-only;
|
|
};
|
|
|
|
partition@2c0000 {
|
|
label = "SBL3";
|
|
reg = <0x02c0000 0x0280000>;
|
|
read-only;
|
|
};
|
|
|
|
partition@540000 {
|
|
label = "DDRCONFIG";
|
|
reg = <0x0540000 0x0120000>;
|
|
read-only;
|
|
};
|
|
|
|
partition@660000 {
|
|
label = "SSD";
|
|
reg = <0x0660000 0x0120000>;
|
|
read-only;
|
|
};
|
|
|
|
partition@780000 {
|
|
label = "TZ";
|
|
reg = <0x0780000 0x0280000>;
|
|
read-only;
|
|
};
|
|
|
|
partition@a00000 {
|
|
label = "RPM";
|
|
reg = <0x0a00000 0x0280000>;
|
|
read-only;
|
|
};
|
|
|
|
art: partition@c80000 {
|
|
label = "art";
|
|
reg = <0x0c80000 0x0140000>;
|
|
read-only;
|
|
};
|
|
|
|
partition@dc0000 {
|
|
label = "APPSBL";
|
|
reg = <0x0dc0000 0x0100000>;
|
|
read-only;
|
|
};
|
|
|
|
partition@ec0000 {
|
|
label = "u_env";
|
|
reg = <0x0ec0000 0x0040000>;
|
|
};
|
|
|
|
partition@f00000 {
|
|
label = "s_env";
|
|
reg = <0x0f00000 0x0040000>;
|
|
};
|
|
|
|
partition@f40000 {
|
|
label = "devinfo";
|
|
reg = <0x0f40000 0x0040000>;
|
|
};
|
|
|
|
partition@f80000 {
|
|
label = "kernel1";
|
|
reg = <0x0f80000 0x2800000>; /* 4 MB, spill to rootfs */
|
|
};
|
|
|
|
partition@1380000 {
|
|
label = "rootfs1";
|
|
reg = <0x1380000 0x2400000>;
|
|
};
|
|
|
|
partition@3780000 {
|
|
label = "kernel2";
|
|
reg = <0x3780000 0x2800000>;
|
|
};
|
|
|
|
partition@3b80000 {
|
|
label = "rootfs2";
|
|
reg = <0x3b80000 0x2400000>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
&mdio0 {
|
|
status = "okay";
|
|
|
|
pinctrl-0 = <&mdio0_pins>;
|
|
pinctrl-names = "default";
|
|
|
|
/* Switch from documentation require at least 10ms for reset */
|
|
reset-gpios = <&qcom_pinmux 63 GPIO_ACTIVE_HIGH>;
|
|
reset-post-delay-us = <12000>;
|
|
|
|
phy0: ethernet-phy@0 {
|
|
reg = <0>;
|
|
qca,ar8327-initvals = <
|
|
0x00004 0x7600000 /* PAD0_MODE */
|
|
0x00008 0x1000000 /* PAD5_MODE */
|
|
0x0000c 0x80 /* PAD6_MODE */
|
|
0x00010 0x2613a0 /* PWS_REG */
|
|
0x000e4 0x6a545 /* MAC_POWER_SEL */
|
|
0x000e0 0xc74164de /* SGMII_CTRL */
|
|
0x0007c 0x4e /* PORT0_STATUS */
|
|
0x00094 0x4e /* PORT6_STATUS */
|
|
>;
|
|
};
|
|
};
|
|
|
|
&gmac1 {
|
|
status = "okay";
|
|
|
|
phy-mode = "rgmii";
|
|
qcom,id = <1>;
|
|
|
|
pinctrl-0 = <&rgmii2_pins>;
|
|
pinctrl-names = "default";
|
|
|
|
fixed-link {
|
|
speed = <1000>;
|
|
full-duplex;
|
|
};
|
|
};
|
|
|
|
&gmac2 {
|
|
status = "okay";
|
|
|
|
phy-mode = "sgmii";
|
|
qcom,id = <2>;
|
|
|
|
fixed-link {
|
|
speed = <1000>;
|
|
full-duplex;
|
|
};
|
|
};
|
|
|
|
&adm_dma {
|
|
status = "okay";
|
|
};
|