95d5a99537
The following adds the Aerohive BR200-WP router to OpenWrt under
the mpc85xx/p1010 subtarget.
Hardware:
- SoC: Freescale P1011
- NOR: Intel JS28F512M29EWH 64MB
- Memory: 2x Nanya NT5TU64M16GG-AC 128MB (Total of 256MB)
- 2.4GHz WiFi: Atheros AR9390-AL1A
- Eth1: Atheros AR8035-A PoE
- 2x LEDs
- 1x Button
- PoE PSE
Flashing:
1. Hook into UART (9600 baud) and enter U-Boot. You may need to enter a
password of administrator or AhNf?d@ta06 if prompted.
2. Once in U-Boot, tftp boot the initramfs image:
dhcp; setenv serverip 192.168.1.3;
tftpboot 0x2004000 openwrt-mpc85xx-p1010-aerohive_br200-wp-initramfs-kernel.bin;
bootm 0x2004000;
3. Once booted, scp over the sysupgrade file and sysupgrade the device
to flash LEDE to the NOR.
Note:
MAC assigns are taken from stock firmware:
Name MAC addr Mode State Chan(Width) VLAN Radio Hive SSID
-------- -------------- -------- ----- ----------- ---- ---------- ---------- ---------
Mgt0 08ea:44XX:XXc0 - U - 1 - hive0 -
Eth0 08ea:44XX:XXc0 wan U - - - - -
Eth1 08ea:44XX:XXc2 access D - - - hive0 -
Eth2 08ea:44XX:XXc3 access D - - - hive0 -
Eth3 08ea:44XX:XXc4 access D - - - hive0 -
Eth4 08ea:44XX:XXc5 access D - - - hive0 -
Wifi0 08ea:44XX:XXd0 access U 1(20MHz) - radio_ng0 - -
Wifi0.1 08ea:44XX:XXd4 access D 1(20MHz) - radio_ng0 hive0 -
Note2:
PoE PSE could be managed with `realtek-poe` package. Example port
config:
config port
option enable '1'
option id '4'
option name 'lan2'
option poe_plus '0'
option priority '2'
config port
option enable '1'
option id '3'
option name 'lan1'
option poe_plus '0'
option priority '1'
Signed-off-by: Pawel Dembicki <paweldembicki@gmail.com>
(switch@0 -> switch@10, Device's quickstart says LEDs are
amber and white => add function+color properties but keep
labels around, use pr_info)
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
374 lines
6.6 KiB
Plaintext
374 lines
6.6 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Aerohive BR200-WP Device Tree Source
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*
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* Based on: Aerohive HiveAP-330 Device Tree Source
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*
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* Copyright (C) 2017 Chris Blake <chrisrblake93@gmail.com>
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* Copyright (C) 2023 Pawel Dembicki <paweldembicki@gmail.com>
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*/
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#include <dt-bindings/leds/common.h>
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/gpio/gpio.h>
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/include/ "fsl/p1020si-pre.dtsi"
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/ {
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model = "Aerohive BR200-WP";
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compatible = "aerohive,br200-wp";
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chosen {
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bootargs = "console=ttyS0,9600";
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bootargs-override = "console=ttyS0,9600 noinitrd";
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};
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aliases {
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led-boot = &led_attention;
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led-failsafe = &led_attention;
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led-running = &led_status;
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led-upgrade = &led_status;
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label-mac-device = &enet0;
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};
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memory {
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device_type = "memory";
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};
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cpus {
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/delete-property/ PowerPC,P1020@1; /* P1011 have one core only */
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};
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board_lbc: lbc: localbus@ffe05000 {
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reg = <0 0xffe05000 0 0x1000>;
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ranges = <0x0 0x0 0x0 0xec000000 0x4000000>;
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nor@0,0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "cfi-flash";
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reg = <0x0 0x0 0x4000000>;
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bank-width = <2>;
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device-width = <1>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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reg = <0x0 0x40000>;
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label = "dtb";
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};
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partition@40000 {
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reg = <0x40000 0x40000>;
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label = "initramfs";
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};
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partition@80000 {
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reg = <0x80000 0x27c0000>;
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label = "rootfs";
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};
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partition@2840000 {
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reg = <0x2840000 0x800000>;
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label = "kernel";
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};
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partition@3040000 {
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reg = <0x3040000 0xec0000>;
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label = "stock-jffs2";
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read-only;
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};
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partition@3f00000 {
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reg = <0x3f00000 0x20000>;
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label = "hw-info";
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read-only;
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compatible = "nvmem-cells";
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#address-cells = <1>;
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#size-cells = <1>;
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macaddr_hwinfo_0: macaddr@0 {
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reg = <0x0 0x6>;
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};
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};
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partition@3f20000 {
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reg = <0x3f20000 0x20000>;
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label = "boot-info";
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read-only;
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};
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partition@3f40000 {
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reg = <0x3f40000 0x20000>;
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label = "boot-info-backup";
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read-only;
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};
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partition@3f60000 {
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reg = <0x3f60000 0x20000>;
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label = "u-boot-env";
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};
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partition@3f80000 {
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reg = <0x3f80000 0x80000>;
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label = "u-boot";
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read-only;
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};
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firmware@0 {
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reg = <0x0 0x3040000>;
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label = "firmware";
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};
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};
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};
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};
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board_soc: soc: soc@ffe00000 {
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ranges = <0x0 0x0 0xffe00000 0x100000>;
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mdio@24000 {
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phy_port1: phy@0 {
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reg = <0>;
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};
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phy_port2: phy@1 {
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reg = <1>;
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};
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phy_port3: phy@2 {
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reg = <2>;
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};
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phy_port4: phy@3 {
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reg = <3>;
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};
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phy_port5: phy@4 {
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reg = <4>;
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};
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switch@10 {
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compatible = "qca,qca8327";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x10>;
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reset-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@1 {
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reg = <1>;
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label = "lan1";
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phy-handle = <&phy_port1>;
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nvmem-cells = <&macaddr_hwinfo_0>;
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nvmem-cell-names = "mac-address";
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mac-address-increment = <2>;
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};
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port@2 {
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reg = <2>;
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label = "lan2";
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phy-handle = <&phy_port2>;
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nvmem-cells = <&macaddr_hwinfo_0>;
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nvmem-cell-names = "mac-address";
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mac-address-increment = <3>;
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};
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port@3 {
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reg = <3>;
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label = "lan3";
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phy-handle = <&phy_port3>;
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nvmem-cells = <&macaddr_hwinfo_0>;
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nvmem-cell-names = "mac-address";
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mac-address-increment = <4>;
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};
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port@4 {
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reg = <4>;
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label = "lan4";
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phy-handle = <&phy_port4>;
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nvmem-cells = <&macaddr_hwinfo_0>;
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nvmem-cell-names = "mac-address";
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mac-address-increment = <5>;
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};
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port@5 {
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reg = <5>;
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label = "wan";
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phy-handle = <&phy_port5>;
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nvmem-cells = <&macaddr_hwinfo_0>;
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nvmem-cell-names = "mac-address";
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};
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port@6 {
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reg = <6>;
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ethernet = <&enet0>;
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phy-mode = "rgmii-id";
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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};
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};
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};
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mdio@25000 {
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status = "disabled";
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};
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mdio@26000 {
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status = "disabled";
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};
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enet0: ethernet@b0000 {
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status = "okay";
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phy-connection-type = "rgmii-id";
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nvmem-cells = <&macaddr_hwinfo_0>;
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nvmem-cell-names = "mac-address";
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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enet1: ethernet@b1000 {
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status = "disabled";
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};
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enet2: ethernet@b2000 {
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status = "disabled";
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};
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gpio0: gpio-controller@fc00 {
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};
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usb@22000 {
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phy_type = "ulpi";
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dr_mode = "host";
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};
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usb@23000 {
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status = "disabled";
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};
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};
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pci0: pcie@ffe09000 {
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status = "disabled";
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};
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pci1: pcie@ffe0a000 {
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reg = <0x0 0xffe0a000 0x0 0x1000>;
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ranges = <0x2000000 0x0 0xc0000000 0x0 0xc0000000 0x0 0x20000000
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0x1000000 0x0 0x00000000 0x0 0xffc20000 0x0 0x10000>;
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reset-gpios = <&gpio0 15 GPIO_ACTIVE_LOW>;
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pcie@0 {
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ranges = <0x2000000 0x0 0xc0000000
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0x2000000 0x0 0xc0000000
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0x0 0x20000000
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0x1000000 0x0 0x0
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0x1000000 0x0 0x0
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0x0 0x100000>;
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ath9k: wifi@0,0 {
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reg = <0x0000 0 0 0 0>;
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#gpio-cells = <2>;
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gpio-controller;
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nvmem-cells = <&macaddr_hwinfo_0>;
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nvmem-cell-names = "mac-address";
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mac-address-increment = <16>;
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};
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};
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};
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leds {
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compatible = "gpio-leds";
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led_attention: led-0 {
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gpios = <&gpio0 11 GPIO_ACTIVE_LOW>;
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label = "amber:status";
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color = <LED_COLOR_ID_AMBER>;
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function = LED_FUNCTION_STATUS;
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};
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led_status: led-1 {
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gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
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label = "white:status";
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color = <LED_COLOR_ID_WHITE>;
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function = LED_FUNCTION_STATUS;
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};
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};
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buttons {
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compatible = "gpio-keys";
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reset {
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label = "Reset button";
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gpios = <&gpio0 8 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_RESTART>;
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};
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};
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};
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/include/ "fsl/p1020si-post.dtsi"
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/ {
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chosen {
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linux,stdout-path = "/soc@ffe00000/serial@4500";
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};
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cpus {
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PowerPC,P1020@0 {
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i-cache-sets = <0x80>;
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i-cache-size = <0x8000>;
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i-cache-block-size = <0x20>;
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d-cache-sets = <0x80>;
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d-cache-size = <0x8000>;
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d-cache-block-size = <0x20>;
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clock-frequency = <0x2756cd00>;
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bus-frequency = <0x13ab6680>;
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timebase-frequency = <0x2756cd0>;
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};
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};
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memory {
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reg = <0x00 0x00 0x00 0x10000000>;
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};
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localbus@ffe05000 {
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bus-frequency = <0x13ab668>;
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};
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soc@ffe00000 {
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bus-frequency = <0x13ab6680>;
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serial@4500 {
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clock-frequency = <0x13ab6680>;
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};
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serial@4600 {
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clock-frequency = <0x13ab6680>;
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};
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};
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pcie@ffe09000 {
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clock-frequency = <0x1fca055>;
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};
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pcie@ffe0a000 {
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clock-frequency = <0x1fca055>;
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};
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};
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