openwrt-cghmn-mt300n/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4029-ap-365.dts

// SPDX-License-Identifier: GPL-2.0-only OR MIT

#include "qcom-ipq4029-aruba-glenmorangie.dtsi"
#include <dt-bindings/gpio/gpio.h>

/ {
	model = "Aruba AP-365";
	compatible = "aruba,ap-365";

	aliases {
		led-boot = &led_system_green;
		led-failsafe = &led_system_red;
		led-running = &led_system_green;
		led-upgrade = &led_system_red;
	};

	leds {
		compatible = "gpio-leds";

		led_system_red: system_red {
			label = "red:system";
			gpios = <&tlmm 46 GPIO_ACTIVE_LOW>;
		};

		led_system_green: system_green {
			label = "green:system";
			gpios = <&tlmm 61 GPIO_ACTIVE_LOW>;
		};

		system_amber {
			label = "amber:system";
			gpios = <&tlmm 49 GPIO_ACTIVE_LOW>;
		};
	};

	watchdog {
		compatible = "linux,wdt-gpio";
		gpios = <&tlmm 41 GPIO_ACTIVE_LOW>;
		hw_algo = "toggle";
		hw_margin_ms = <1000>;
		always-running;
	};
};

&tlmm {
	/*
	 * In addition to the Pins listed below,
	 * the following GPIOs have "features":
	 * 39 - out - pulse low to reset watchdog status flipflop
	 * 40 - out - active high to enable watchdog
	 * 41 - out - watchdog poke
	 * 42 - out - active low to reset BLE radio
	 * 43 - out - active low to reset TPM
	 * 47 - out - pulse low to reset warm reset status
	 * 54 - out - active low to force HW reset
	 * 18 - in  - PHY interrupt line
	 * 45 - in  - power monitor interrupt
	 * 48 - in  - active low when cold reset
	 * 52 - in  - active high when watchdog reset
	 */

	phy-reset {
		line-name = "PHY-reset";
		gpios = <42 GPIO_ACTIVE_HIGH>;
		gpio-hog;
		output-high;
	};
};

&i2c_0 {
	power-monitor@40 {
		/* No driver */
		compatible = "isl,isl28022";
		reg = <0x40>;
	};

	temperature-sensor@48 {
		compatible = "adi,ad7416";
		reg = <0x48>;
	};
};

&blsp1_spi1 {
	pinctrl-0 = <&spi_0_pins>;
	pinctrl-names = "default";
	status = "okay";
	cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;

	flash@0 {
		compatible = "jedec,spi-nor";
		reg = <0>;
		spi-max-frequency = <24000000>;

		partitions {
			compatible = "fixed-partitions";
			#address-cells = <1>;
			#size-cells = <1>;

			/*
			 * There is no partition map for the NOR flash
			 * in the stock firmware.
			 *
			 * All partitions here are based on offsets
			 * found in the U-Boot GPL code and information
			 * from smem.
			 */

			partition@0 {
				label = "sbl1";
				reg = <0x0 0x40000>;
				read-only;
			};

			partition@40000 {
				label = "mibib";
				reg = <0x40000 0x20000>;
				read-only;
			};

			partition@60000 {
				label = "qsee";
				reg = <0x60000 0x60000>;
				read-only;
			};

			partition@c0000 {
				label = "cdt";
				reg = <0xc0000 0x10000>;
				read-only;
			};

			partition@d0000 {
				label = "ddrparams";
				reg = <0xd0000 0x10000>;
				read-only;
			};

			partition@e0000 {
				label = "u-boot-env";
				reg = <0xe0000 0x10000>;
			};

			partition@f0000 {
				label = "appsbl";
				reg = <0xf0000 0x100000>;
				read-only;
			};

			partition@1f0000 {
				label = "ART";
				reg = <0x1f0000 0x10000>;
				read-only;
				compatible = "nvmem-cells";
				#address-cells = <1>;
				#size-cells = <1>;

				precal_art_1000: precal@1000 {
					reg = <0x1000 0x2f20>;
				};

				precal_art_5000: precal@5000 {
					reg = <0x5000 0x2f20>;
				};
			};

			partition@200000 {
				label = "osss";
				reg = <0x200000 0x170000>;
				read-only;
			};

			partition@370000 {
				label = "pds";
				reg = <0x370000 0x10000>;
				read-only;
			};

			partition@380000 {
				label = "apcd";
				reg = <0x380000 0x10000>;
				read-only;
			};

			partition@390000 {
				label = "mfginfo";
				reg = <0x390000 0x10000>;
				read-only;
				compatible = "nvmem-cells";
				#address-cells = <1>;
				#size-cells = <1>;

				macaddr_mfginfo_1d: macaddr@1d {
					reg = <0x1d 0x6>;
				};
			};

			partition@3a0000 {
				label = "fcache";
				reg = <0x3a0000 0x10000>;
				read-only;
			};

			partition@3b0000 {
				label = "osss1";
				reg = <0x3b0000 0x50000>;
				read-only;
			};
		};
	};
};