748682e855
Changelog: https://cdn.kernel.org/pub/linux/kernel/v6.x/ChangeLog-6.6.83 Removed upstreamed: bcm27xx/patches-6.6/950-0483-usb-xhci-borrow-upstream-TRB_FETCH-quirk-on-VL805-ho.patch[1] Manually rebased: bcm27xx/patches-6.6/950-0061-Revert-Revert-xhci-add-quirk-for-host-controllers-th.patch bcm27xx/patches-6.6/950-0485-usb-xhci-add-XHCI_VLI_HUB_TT_QUIRK.patch bcm27xx/patches-6.6/950-0519-usb-dwc3-Set-DMA-and-coherent-masks-early.patch All other patches automatically rebased. 1. https://web.git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/drivers/usb/host/xhci-pci.c?h=linux-6.6.y&id=c401b1b4b835d66792e884b76264d742a20d931d Build system: x86/64 Build-tested: x86/64 Run-tested: x86/64 Signed-off-by: John Audia <therealgraysky@proton.me> [fixed issues with bcm27xx patches] Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
92 lines
2.7 KiB
Diff
92 lines
2.7 KiB
Diff
From 97789b93b792fc97ad4476b79e0f38ffa8e7e0ee Mon Sep 17 00:00:00 2001
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From: Sebastian Reichel <sebastian.reichel@collabora.com>
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Date: Fri, 20 Oct 2023 16:11:41 +0200
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Subject: [PATCH] usb: dwc3: add optional PHY interface clocks
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On Rockchip RK3588 one of the DWC3 cores is integrated weirdly and
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requires two extra clocks to be enabled. Without these extra clocks
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hot-plugging USB devices is broken.
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Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
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Acked-by: Thinh Nguyen <Thinh.Nguyen@synopsys.com>
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Link: https://lore.kernel.org/r/20231020150022.48725-3-sebastian.reichel@collabora.com
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Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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---
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drivers/usb/dwc3/core.c | 28 ++++++++++++++++++++++++++++
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drivers/usb/dwc3/core.h | 4 ++++
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2 files changed, 32 insertions(+)
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--- a/drivers/usb/dwc3/core.c
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+++ b/drivers/usb/dwc3/core.c
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@@ -860,8 +860,20 @@ static int dwc3_clk_enable(struct dwc3 *
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if (ret)
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goto disable_ref_clk;
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+ ret = clk_prepare_enable(dwc->utmi_clk);
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+ if (ret)
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+ goto disable_susp_clk;
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+
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+ ret = clk_prepare_enable(dwc->pipe_clk);
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+ if (ret)
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+ goto disable_utmi_clk;
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+
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return 0;
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+disable_utmi_clk:
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+ clk_disable_unprepare(dwc->utmi_clk);
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+disable_susp_clk:
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+ clk_disable_unprepare(dwc->susp_clk);
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disable_ref_clk:
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clk_disable_unprepare(dwc->ref_clk);
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disable_bus_clk:
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@@ -871,6 +883,8 @@ disable_bus_clk:
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static void dwc3_clk_disable(struct dwc3 *dwc)
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{
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+ clk_disable_unprepare(dwc->pipe_clk);
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+ clk_disable_unprepare(dwc->utmi_clk);
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clk_disable_unprepare(dwc->susp_clk);
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clk_disable_unprepare(dwc->ref_clk);
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clk_disable_unprepare(dwc->bus_clk);
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@@ -1886,6 +1900,20 @@ static int dwc3_get_clocks(struct dwc3 *
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}
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}
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+ /* specific to Rockchip RK3588 */
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+ dwc->utmi_clk = devm_clk_get_optional(dev, "utmi");
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+ if (IS_ERR(dwc->utmi_clk)) {
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+ return dev_err_probe(dev, PTR_ERR(dwc->utmi_clk),
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+ "could not get utmi clock\n");
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+ }
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+
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+ /* specific to Rockchip RK3588 */
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+ dwc->pipe_clk = devm_clk_get_optional(dev, "pipe");
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+ if (IS_ERR(dwc->pipe_clk)) {
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+ return dev_err_probe(dev, PTR_ERR(dwc->pipe_clk),
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+ "could not get pipe clock\n");
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+ }
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+
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return 0;
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}
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--- a/drivers/usb/dwc3/core.h
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+++ b/drivers/usb/dwc3/core.h
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@@ -1003,6 +1003,8 @@ struct dwc3_scratchpad_array {
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* @bus_clk: clock for accessing the registers
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* @ref_clk: reference clock
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* @susp_clk: clock used when the SS phy is in low power (S3) state
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+ * @utmi_clk: clock used for USB2 PHY communication
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+ * @pipe_clk: clock used for USB3 PHY communication
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* @reset: reset control
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* @regs: base address for our registers
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* @regs_size: address space size
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@@ -1175,6 +1177,8 @@ struct dwc3 {
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struct clk *bus_clk;
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struct clk *ref_clk;
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struct clk *susp_clk;
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+ struct clk *utmi_clk;
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+ struct clk *pipe_clk;
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struct reset_control *reset;
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