08becaf62f
There is a custom LED controller between the 3 SoC GPIO outputs and the red and blue LEDs of the device. It implements a strange mapping that includes fixed, flashing, and breathing modes. The current DTS configuration causes OpenWrt to flash the LEDs over the controller's own flashing, resulting in chaotic output in boot, failsafe, and upgrade modes. This change fixes the LEDs in the best way possible as long as each OpenWrt running state is limited to be signaled by a single led. Signed-off-by: Rodrigo Balerdi <lanchon@gmail.com> Link: https://github.com/openwrt/openwrt/pull/15440 Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> (cherry picked from commit 0868268c9fd4397411e9629eedda35b1547e798e)
420 lines
7.0 KiB
Plaintext
420 lines
7.0 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-or-later
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#include "qcom-ipq8065-smb208.dtsi"
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#include <dt-bindings/input/input.h>
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/ {
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model = "Askey RT4230W REV6";
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compatible = "askey,rt4230w-rev6", "qcom,ipq8065", "qcom,ipq8064";
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memory@0 {
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reg = <0x42000000 0x3e000000>;
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device_type = "memory";
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};
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aliases {
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led-boot = &ledctrl1;
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led-failsafe = &ledctrl1;
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led-running = &ledctrl3;
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led-upgrade = &ledctrl1;
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};
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chosen {
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bootargs = "rootfstype=squashfs noinitrd";
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};
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keys {
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compatible = "gpio-keys";
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pinctrl-0 = <&button_pins>;
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pinctrl-names = "default";
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reset {
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label = "reset";
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gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_RESTART>;
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};
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wps {
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label = "wps";
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gpios = <&qcom_pinmux 68 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_WPS_BUTTON>;
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};
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};
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leds {
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compatible = "gpio-leds";
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pinctrl-0 = <&led_pins>;
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pinctrl-names = "default";
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ledctrl1: ledctrl1 {
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label = "ledctrl1";
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gpios = <&qcom_pinmux 22 GPIO_ACTIVE_HIGH>;
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};
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ledctrl2: ledctrl2 {
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label = "ledctrl2";
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gpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>;
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linux,default-trigger = "default-on";
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};
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ledctrl3: ledctrl3 {
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label = "ledctrl3";
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gpios = <&qcom_pinmux 24 GPIO_ACTIVE_HIGH>;
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};
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};
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};
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&qcom_pinmux {
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button_pins: button_pins {
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mux {
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pins = "gpio54", "gpio68";
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function = "gpio";
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drive-strength = <2>;
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bias-pull-up;
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};
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};
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led_pins: led_pins {
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mux {
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pins = "gpio22", "gpio23", "gpio24";
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function = "gpio";
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drive-strength = <2>;
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bias-pull-down;
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};
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};
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rgmii2_pins: rgmii2-pins {
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mux {
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pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31",
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"gpio51", "gpio52", "gpio59", "gpio60", "gpio61", "gpio62";
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function = "rgmii2";
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drive-strength = <8>;
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bias-disable;
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};
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tx {
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pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32";
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input-disable;
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};
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};
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spi_pins: spi_pins {
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cs {
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pins = "gpio20";
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drive-strength = <12>;
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};
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};
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};
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&gsbi5 {
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qcom,mode = <GSBI_PROT_SPI>;
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status = "okay";
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spi@1a280000 {
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status = "okay";
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pinctrl-0 = <&spi_pins>;
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pinctrl-names = "default";
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cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>;
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flash@0 {
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compatible = "everspin,mr25h256";
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#address-cells = <1>;
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#size-cells = <1>;
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spi-max-frequency = <40000000>;
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reg = <0>;
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};
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};
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};
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&nand {
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status = "okay";
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nand@0 {
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reg = <0>;
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compatible = "qcom,nandcs";
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nand-ecc-strength = <4>;
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nand-bus-width = <8>;
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nand-ecc-step-size = <512>;
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qcom,boot-partitions = <0x0 0x1180000 0x1340000 0x10c0000>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "0:SBL1";
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reg = <0x0000000 0x0040000>;
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read-only;
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};
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partition@40000 {
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label = "0:MIBIB";
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reg = <0x0040000 0x0140000>;
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read-only;
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};
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partition@180000 {
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label = "0:SBL2";
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reg = <0x0180000 0x0140000>;
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read-only;
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};
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partition@2c0000 {
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label = "0:SBL3";
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reg = <0x02c0000 0x0280000>;
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read-only;
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};
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partition@540000 {
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label = "0:DDRCONFIG";
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reg = <0x0540000 0x0120000>;
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read-only;
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};
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partition@660000 {
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label = "0:SSD";
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reg = <0x0660000 0x0120000>;
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read-only;
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};
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partition@780000 {
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label = "0:TZ";
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reg = <0x0780000 0x0280000>;
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read-only;
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};
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partition@a00000 {
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label = "0:RPM";
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reg = <0x0a00000 0x0280000>;
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read-only;
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};
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partition@c80000 {
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label = "0:APPSBL";
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reg = <0x0c80000 0x0500000>;
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read-only;
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};
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partition@1180000 {
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label = "0:APPSBLENV";
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reg = <0x1180000 0x0080000>;
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};
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partition@1200000 {
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label = "0:ART";
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reg = <0x1200000 0x0140000>;
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read-only;
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compatible = "nvmem-cells";
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#address-cells = <1>;
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#size-cells = <1>;
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macaddr_ART_0: macaddr@0 {
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reg = <0x0 0x6>;
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};
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macaddr_ART_6: macaddr@6 {
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reg = <0x6 0x6>;
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};
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precal_ART_1000: precal@1000 {
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reg = <0x1000 0x2f20>;
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};
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precal_ART_5000: precal@5000 {
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reg = <0x5000 0x2f20>;
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};
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};
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partition@1340000 {
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label = "0:BOOTCONFIG";
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reg = <0x1340000 0x0060000>;
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read-only;
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};
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partition@13a0000 {
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label = "0:SBL2_1";
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reg = <0x13a0000 0x0140000>;
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read-only;
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};
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partition@14e0000 {
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label = "0:SBL3_1";
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reg = <0x14e0000 0x0280000>;
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read-only;
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};
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partition@1760000 {
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label = "0:DDRCONFIG_1";
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reg = <0x1760000 0x0120000>;
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read-only;
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};
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partition@1880000 {
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label = "0:SSD_1";
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reg = <0x1880000 0x0120000>;
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read-only;
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};
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partition@19a0000 {
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label = "0:TZ_1";
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reg = <0x19a0000 0x0280000>;
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read-only;
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};
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partition@1c20000 {
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label = "0:RPM_1";
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reg = <0x1c20000 0x0280000>;
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read-only;
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};
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partition@1ea0000 {
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label = "0:BOOTCONFIG1";
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reg = <0x1ea0000 0x0060000>;
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read-only;
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};
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partition@1f00000 {
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label = "0:APPSBL_1";
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reg = <0x1f00000 0x0500000>;
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read-only;
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};
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partition@2400000 {
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label = "ubi";
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reg = <0x2400000 0x1a000000>;
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};
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};
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};
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};
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&mdio0 {
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status = "okay";
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pinctrl-0 = <&mdio0_pins>;
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pinctrl-names = "default";
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phy0: ethernet-phy@0 {
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reg = <0x0>;
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qca,ar8327-initvals = <
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0x00004 0x7600000 /* PAD0_MODE */
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0x00008 0x1000000 /* PAD5_MODE */
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0x0000c 0x80 /* PAD6_MODE */
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0x000e4 0xaa545 /* MAC_POWER_SEL */
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0x000e0 0xc74164de /* SGMII_CTRL */
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0x0007c 0x4e /* PORT0_STATUS */
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0x00094 0x4e /* PORT6_STATUS */
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0x00050 0xcf02cf02 /* LED_CTRL_0 */
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0x00054 0xc832c832 /* LED_CTRL_1 */
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>;
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};
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};
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&gmac0 {
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status = "okay";
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phy-mode = "rgmii";
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qcom,id = <0>;
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nvmem-cells = <&macaddr_ART_0>;
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nvmem-cell-names = "mac-address";
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pinctrl-0 = <&rgmii2_pins>;
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pinctrl-names = "default";
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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&gmac1 {
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status = "okay";
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phy-mode = "sgmii";
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qcom,id = <1>;
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nvmem-cells = <&macaddr_ART_6>;
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nvmem-cell-names = "mac-address";
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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&adm_dma {
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status = "okay";
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};
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&hs_phy_0 {
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status = "okay";
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};
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&ss_phy_0 {
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status = "okay";
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};
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&usb3_0 {
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status = "okay";
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};
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&hs_phy_1 {
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status = "okay";
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};
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&ss_phy_1 {
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status = "okay";
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};
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&usb3_1 {
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status = "okay";
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};
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&pcie0 {
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status = "okay";
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reset-gpio = <&qcom_pinmux 3 GPIO_ACTIVE_HIGH>;
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pinctrl-0 = <&pcie0_pins>;
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pinctrl-names = "default";
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bridge@0,0 {
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reg = <0x00000000 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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ranges;
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wifi0: wifi@1,0 {
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compatible = "pci168c,0046";
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reg = <0x00010000 0 0 0 0>;
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nvmem-cells = <&precal_ART_1000>;
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nvmem-cell-names = "pre-calibration";
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};
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};
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};
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&pcie1 {
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status = "okay";
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reset-gpio = <&qcom_pinmux 48 GPIO_ACTIVE_HIGH>;
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pinctrl-0 = <&pcie1_pins>;
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pinctrl-names = "default";
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max-link-speed = <1>;
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bridge@0,0 {
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reg = <0x00000000 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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ranges;
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wifi1: wifi@1,0 {
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compatible = "pci168c,0046";
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reg = <0x00010000 0 0 0 0>;
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nvmem-cells = <&precal_ART_5000>;
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nvmem-cell-names = "pre-calibration";
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};
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};
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};
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