cfca9d6894
The redundant xtal clock source caused clock registration failure. Link: https://lore.kernel.org/all/20250108093636.265033-1-sergio.paracuellos@gmail.com/ Fixes: https://github.com/openwrt/openwrt/issues/17677 Signed-off-by: Shiji Yang <yangshiji66@qq.com> Link: https://github.com/openwrt/openwrt/pull/17830 Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
29 lines
1.0 KiB
Diff
29 lines
1.0 KiB
Diff
From 830d8062d25581cf0beaa334486eea06834044da Mon Sep 17 00:00:00 2001
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From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
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Date: Wed, 8 Jan 2025 10:36:36 +0100
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Subject: [PATCH] clk: ralink: mtmips: remove duplicated 'xtal' clock for
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Ralink SoC RT3883
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Ralink SoC RT3883 has already 'xtal' defined as a base clock so there is no
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need to redefine it again in fixed clocks section. Hence, remove the duplicate
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one from there.
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Fixes: d34db686a3d7 ("clk: ralink: mtmips: fix clocks probe order in oldest ralink SoCs")
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Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
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Link: https://lore.kernel.org/r/20250108093636.265033-1-sergio.paracuellos@gmail.com
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Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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---
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drivers/clk/ralink/clk-mtmips.c | 1 -
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1 file changed, 1 deletion(-)
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--- a/drivers/clk/ralink/clk-mtmips.c
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+++ b/drivers/clk/ralink/clk-mtmips.c
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@@ -266,7 +266,6 @@ err_clk_unreg:
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}
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static struct mtmips_clk_fixed rt3883_fixed_clocks[] = {
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- CLK_FIXED("xtal", NULL, 40000000),
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CLK_FIXED("periph", "xtal", 40000000)
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};
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