93173aee96
Add initial support for new target with the initial patch for ethernet support using pending upstream patches for PCS UNIPHY, PPE and EDMA. Only initramfs currently working as support for new SPI/NAND implementation, USB, CPUFreq and other devices is still unfinished and needs to be evaluated. Link: https://github.com/openwrt/openwrt/pull/17725 Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
232 lines
5.8 KiB
Diff
232 lines
5.8 KiB
Diff
From 9f3d547ccaf1113244f9aeb1a849e553321869ea Mon Sep 17 00:00:00 2001
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From: Lei Wei <quic_leiwei@quicinc.com>
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Date: Tue, 14 May 2024 10:53:27 +0800
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Subject: [PATCH 17/17] arm64: dts: qcom: Add IPQ9574 RDP433 port node
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There are 6 PPE MAC ports available on RDP433. The port1-port4 are
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connected with QCA8075 QUAD PHYs through UNIPHY0 PCS channel0-channel3.
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The port5 is connected with Aquantia PHY through UNIPHY1 PCS channel0
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and the port6 is connected with Aquantia PHY through UNIPHY2 PCS
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channel0.
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Change-Id: Ic16efdef2fe2cff7b1e80245619c0f82afb24cb9
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Signed-off-by: Lei Wei <quic_leiwei@quicinc.com>
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---
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arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts | 169 +++++++++++++++++++-
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arch/arm64/boot/dts/qcom/ipq9574.dtsi | 2 +-
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2 files changed, 169 insertions(+), 2 deletions(-)
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diff --git a/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts b/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts
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index 1bb8d96c9a82..1bbe4c258c15 100644
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--- a/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts
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+++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts
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@@ -3,11 +3,13 @@
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* IPQ9574 RDP433 board device tree source
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*
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* Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
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- * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
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+ * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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/dts-v1/;
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+#include <dt-bindings/gpio/gpio.h>
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+
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#include "ipq9574-rdp-common.dtsi"
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/ {
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@@ -15,6 +15,46 @@ / {
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compatible = "qcom,ipq9574-ap-al02-c7", "qcom,ipq9574";
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};
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+&mdio {
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+ reset-gpios = <&tlmm 60 GPIO_ACTIVE_LOW>;
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+ clock-frequency = <6250000>;
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+ status = "okay";
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+
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+ ethernet-phy-package@0 {
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+ compatible = "qcom,qca8075-package";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ reg = <0x10>;
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+ qcom,package-mode = "qsgmii";
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+
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+ phy0: ethernet-phy@10 {
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+ reg = <0x10>;
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+ };
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+
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+ phy1: ethernet-phy@11 {
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+ reg = <0x11>;
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+ };
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+
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+ phy2: ethernet-phy@12 {
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+ reg = <0x12>;
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+ };
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+
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+ phy3: ethernet-phy@13 {
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+ reg = <0x13>;
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+ };
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+ };
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+
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+ phy4: ethernet-phy@8 {
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+ compatible ="ethernet-phy-ieee802.3-c45";
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+ reg = <8>;
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+ };
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+
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+ phy5: ethernet-phy@0 {
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+ compatible ="ethernet-phy-ieee802.3-c45";
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+ reg = <0>;
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+ };
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+};
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+
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&sdhc_1 {
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pinctrl-0 = <&sdc_default_state>;
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pinctrl-names = "default";
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@@ -60,3 +100,130 @@ rclk-pins {
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};
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};
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};
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+
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+&qcom_ppe {
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+ ethernet-ports {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ port@1 {
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+ reg = <1>;
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+ phy-mode = "qsgmii";
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+ managed = "in-band-status";
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+ phy-handle = <&phy0>;
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+ pcs-handle = <&pcsuniphy0_ch0>;
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+ clocks = <&nsscc NSS_CC_PORT1_MAC_CLK>,
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+ <&nsscc NSS_CC_PORT1_RX_CLK>,
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+ <&nsscc NSS_CC_PORT1_TX_CLK>;
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+ clock-names = "port_mac",
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+ "port_rx",
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+ "port_tx";
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+ resets = <&nsscc PORT1_MAC_ARES>,
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+ <&nsscc PORT1_RX_ARES>,
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+ <&nsscc PORT1_TX_ARES>;
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+ reset-names = "port_mac",
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+ "port_rx",
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+ "port_tx";
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+ };
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+
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+ port@2 {
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+ reg = <2>;
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+ phy-mode = "qsgmii";
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+ managed = "in-band-status";
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+ phy-handle = <&phy1>;
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+ pcs-handle = <&pcsuniphy0_ch1>;
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+ clocks = <&nsscc NSS_CC_PORT2_MAC_CLK>,
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+ <&nsscc NSS_CC_PORT2_RX_CLK>,
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+ <&nsscc NSS_CC_PORT2_TX_CLK>;
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+ clock-names = "port_mac",
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+ "port_rx",
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+ "port_tx";
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+ resets = <&nsscc PORT2_MAC_ARES>,
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+ <&nsscc PORT2_RX_ARES>,
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+ <&nsscc PORT2_TX_ARES>;
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+ reset-names = "port_mac",
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+ "port_rx",
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+ "port_tx";
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+ };
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+
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+ port@3 {
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+ reg = <3>;
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+ phy-mode = "qsgmii";
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+ managed = "in-band-status";
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+ phy-handle = <&phy2>;
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+ pcs-handle = <&pcsuniphy0_ch2>;
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+ clocks = <&nsscc NSS_CC_PORT3_MAC_CLK>,
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+ <&nsscc NSS_CC_PORT3_RX_CLK>,
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+ <&nsscc NSS_CC_PORT3_TX_CLK>;
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+ clock-names = "port_mac",
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+ "port_rx",
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+ "port_tx";
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+ resets = <&nsscc PORT3_MAC_ARES>,
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+ <&nsscc PORT3_RX_ARES>,
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+ <&nsscc PORT3_TX_ARES>;
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+ reset-names = "port_mac",
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+ "port_rx",
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+ "port_tx";
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+ };
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+
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+ port@4 {
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+ reg = <4>;
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+ phy-mode = "qsgmii";
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+ managed = "in-band-status";
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+ phy-handle = <&phy3>;
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+ pcs-handle = <&pcsuniphy0_ch3>;
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+ clocks = <&nsscc NSS_CC_PORT4_MAC_CLK>,
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+ <&nsscc NSS_CC_PORT4_RX_CLK>,
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+ <&nsscc NSS_CC_PORT4_TX_CLK>;
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+ clock-names = "port_mac",
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+ "port_rx",
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+ "port_tx";
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+ resets = <&nsscc PORT4_MAC_ARES>,
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+ <&nsscc PORT4_RX_ARES>,
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+ <&nsscc PORT4_TX_ARES>;
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+ reset-names = "port_mac",
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+ "port_rx",
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+ "port_tx";
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+ };
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+
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+ port@5 {
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+ reg = <5>;
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+ phy-mode = "usxgmii";
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+ managed = "in-band-status";
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+ phy-handle = <&phy4>;
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+ pcs-handle = <&pcsuniphy1_ch0>;
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+ clocks = <&nsscc NSS_CC_PORT5_MAC_CLK>,
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+ <&nsscc NSS_CC_PORT5_RX_CLK>,
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+ <&nsscc NSS_CC_PORT5_TX_CLK>;
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+ clock-names = "port_mac",
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+ "port_rx",
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+ "port_tx";
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+ resets = <&nsscc PORT5_MAC_ARES>,
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+ <&nsscc PORT5_RX_ARES>,
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+ <&nsscc PORT5_TX_ARES>;
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+ reset-names = "port_mac",
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+ "port_rx",
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+ "port_tx";
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+ };
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+
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+ port@6 {
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+ reg = <6>;
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+ phy-mode = "usxgmii";
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+ managed = "in-band-status";
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+ phy-handle = <&phy5>;
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+ pcs-handle = <&pcsuniphy2_ch0>;
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+ clocks = <&nsscc NSS_CC_PORT6_MAC_CLK>,
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+ <&nsscc NSS_CC_PORT6_RX_CLK>,
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+ <&nsscc NSS_CC_PORT6_TX_CLK>;
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+ clock-names = "port_mac",
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+ "port_rx",
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+ "port_tx";
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+ resets = <&nsscc PORT6_MAC_ARES>,
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+ <&nsscc PORT6_RX_ARES>,
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+ <&nsscc PORT6_TX_ARES>;
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+ reset-names = "port_mac",
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+ "port_rx",
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+ "port_tx";
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+ };
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+ };
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+};
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diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
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index 61f9a7ee7282..5c7b47979b79 100644
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--- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
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+++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
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@@ -903,7 +903,7 @@ pcsuniphy2_ch0: uniphy-ch@0 {
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};
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};
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- ethernet@3a000000 {
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+ qcom_ppe: ethernet@3a000000 {
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compatible = "qcom,ipq9574-ppe";
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reg = <0x3a000000 0xbef800>;
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ranges;
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--
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2.45.2
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