93173aee96
Add initial support for new target with the initial patch for ethernet support using pending upstream patches for PCS UNIPHY, PPE and EDMA. Only initramfs currently working as support for new SPI/NAND implementation, USB, CPUFreq and other devices is still unfinished and needs to be evaluated. Link: https://github.com/openwrt/openwrt/pull/17725 Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
152 lines
5.2 KiB
Diff
152 lines
5.2 KiB
Diff
From a36607b554841358733167483d194ae7d3969444 Mon Sep 17 00:00:00 2001
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From: Pavithra R <quic_pavir@quicinc.com>
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Date: Tue, 11 Jun 2024 01:43:22 +0530
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Subject: [PATCH 45/50] net: ethernet: qualcomm: Add sysctl for RPS bitmap
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Add sysctl to configure RPS bitmap for EDMA receive.
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This bitmap is used to configure the set of ARM cores
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used to receive packets from EDMA.
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Change-Id: Ie0e7d5971db93ea1494608a9e79c4abb13ce69b6
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Signed-off-by: Pavithra R <quic_pavir@quicinc.com>
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---
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drivers/net/ethernet/qualcomm/ppe/edma.c | 23 ++++++++++++++++
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drivers/net/ethernet/qualcomm/ppe/edma.h | 2 ++
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.../net/ethernet/qualcomm/ppe/edma_cfg_rx.c | 27 +++++++++++++++++++
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.../net/ethernet/qualcomm/ppe/edma_cfg_rx.h | 4 +++
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4 files changed, 56 insertions(+)
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diff --git a/drivers/net/ethernet/qualcomm/ppe/edma.c b/drivers/net/ethernet/qualcomm/ppe/edma.c
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index ae9ca528fd55..428c7b134feb 100644
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--- a/drivers/net/ethernet/qualcomm/ppe/edma.c
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+++ b/drivers/net/ethernet/qualcomm/ppe/edma.c
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@@ -797,6 +797,11 @@ void edma_destroy(struct ppe_device *ppe_dev)
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struct edma_ring_info *rx = hw_info->rx;
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u32 i;
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+ if (edma_ctx->rx_rps_ctl_table_hdr) {
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+ unregister_sysctl_table(edma_ctx->rx_rps_ctl_table_hdr);
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+ edma_ctx->rx_rps_ctl_table_hdr = NULL;
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+ }
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+
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/* Disable interrupts. */
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for (i = 1; i <= hw_info->max_ports; i++)
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edma_cfg_tx_disable_interrupts(i);
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@@ -840,6 +845,17 @@ void edma_destroy(struct ppe_device *ppe_dev)
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kfree(edma_ctx->netdev_arr);
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}
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+/* EDMA Rx RPS core sysctl table */
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+static struct ctl_table edma_rx_rps_core_table[] = {
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+ {
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+ .procname = "rps_bitmap_cores",
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+ .data = &edma_cfg_rx_rps_bitmap_cores,
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+ .maxlen = sizeof(int),
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+ .mode = 0644,
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+ .proc_handler = edma_cfg_rx_rps_bitmap
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+ },
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+};
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+
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/**
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* edma_setup - EDMA Setup.
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* @ppe_dev: PPE device
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@@ -865,6 +881,13 @@ int edma_setup(struct ppe_device *ppe_dev)
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if (tx_requeue_stop != 0)
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edma_ctx->tx_requeue_stop = true;
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+ edma_ctx->rx_rps_ctl_table_hdr = register_sysctl("net/edma",
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+ edma_rx_rps_core_table);
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+ if (!edma_ctx->rx_rps_ctl_table_hdr) {
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+ pr_err("Rx rps sysctl table configuration failed\n");
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+ return -EINVAL;
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+ }
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+
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/* Configure the EDMA common clocks. */
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ret = edma_clock_init();
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if (ret) {
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diff --git a/drivers/net/ethernet/qualcomm/ppe/edma.h b/drivers/net/ethernet/qualcomm/ppe/edma.h
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index ac6d2fcc2983..3f3d253476f6 100644
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--- a/drivers/net/ethernet/qualcomm/ppe/edma.h
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+++ b/drivers/net/ethernet/qualcomm/ppe/edma.h
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@@ -122,6 +122,7 @@ struct edma_intr_info {
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* @tx_rings: Tx Descriptor Ring, SW is producer
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* @txcmpl_rings: Tx complete Ring, SW is consumer
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* @err_stats: Per CPU error statistics
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+ * @rx_rps_ctl_table_hdr: Rx RPS sysctl table
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* @rx_page_mode: Page mode enabled or disabled
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* @rx_buf_size: Rx buffer size for Jumbo MRU
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* @tx_requeue_stop: Tx requeue stop enabled or disabled
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@@ -137,6 +138,7 @@ struct edma_context {
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struct edma_txdesc_ring *tx_rings;
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struct edma_txcmpl_ring *txcmpl_rings;
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struct edma_err_stats __percpu *err_stats;
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+ struct ctl_table_header *rx_rps_ctl_table_hdr;
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u32 rx_page_mode;
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u32 rx_buf_size;
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bool tx_requeue_stop;
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diff --git a/drivers/net/ethernet/qualcomm/ppe/edma_cfg_rx.c b/drivers/net/ethernet/qualcomm/ppe/edma_cfg_rx.c
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index bf8854976328..58021df6c950 100644
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--- a/drivers/net/ethernet/qualcomm/ppe/edma_cfg_rx.c
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+++ b/drivers/net/ethernet/qualcomm/ppe/edma_cfg_rx.c
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@@ -43,6 +43,8 @@ static u32 edma_rx_ring_queue_map[][EDMA_MAX_CORE] = {{ 0, 8, 16, 24 },
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{ 6, 14, 22, 30 },
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{ 7, 15, 23, 31 }};
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+u32 edma_cfg_rx_rps_bitmap_cores = EDMA_RX_DEFAULT_BITMAP;
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+
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static int edma_cfg_rx_desc_rings_reset_queue_mapping(void)
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{
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struct edma_hw_info *hw_info = edma_ctx->hw_info;
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@@ -987,3 +989,28 @@ int edma_cfg_rx_rps_hash_map(void)
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return 0;
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}
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+
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+/* Configure RPS hash mapping based on bitmap */
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+int edma_cfg_rx_rps_bitmap(struct ctl_table *table, int write,
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+ void *buffer, size_t *lenp, loff_t *ppos)
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+{
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+ int ret;
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+
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+ ret = proc_dointvec(table, write, buffer, lenp, ppos);
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+
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+ if (!write)
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+ return ret;
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+
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+ if (!edma_cfg_rx_rps_bitmap_cores ||
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+ edma_cfg_rx_rps_bitmap_cores > EDMA_RX_DEFAULT_BITMAP) {
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+ pr_warn("Incorrect CPU bitmap: %x. Setting it to default value: %d",
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+ edma_cfg_rx_rps_bitmap_cores, EDMA_RX_DEFAULT_BITMAP);
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+ edma_cfg_rx_rps_bitmap_cores = EDMA_RX_DEFAULT_BITMAP;
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+ }
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+
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+ ret = edma_cfg_rx_rps_hash_map();
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+
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+ pr_info("EDMA RPS bitmap value: %d\n", edma_cfg_rx_rps_bitmap_cores);
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+
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+ return ret;
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+}
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diff --git a/drivers/net/ethernet/qualcomm/ppe/edma_cfg_rx.h b/drivers/net/ethernet/qualcomm/ppe/edma_cfg_rx.h
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index bd897dba286a..53d2e6b39794 100644
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--- a/drivers/net/ethernet/qualcomm/ppe/edma_cfg_rx.h
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+++ b/drivers/net/ethernet/qualcomm/ppe/edma_cfg_rx.h
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@@ -49,6 +49,8 @@
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/* Default bitmap of cores for RPS to ARM cores */
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#define EDMA_RX_DEFAULT_BITMAP ((1 << EDMA_MAX_CORE) - 1)
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+extern u32 edma_cfg_rx_rps_bitmap_cores;
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+
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int edma_cfg_rx_rings(void);
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int edma_cfg_rx_rings_alloc(void);
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void edma_cfg_rx_ring_mappings(void);
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@@ -66,4 +68,6 @@ void edma_cfg_rx_buff_size_setup(void);
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int edma_cfg_rx_rps_hash_map(void);
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int edma_cfg_rx_rps(struct ctl_table *table, int write,
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void *buffer, size_t *lenp, loff_t *ppos);
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+int edma_cfg_rx_rps_bitmap(struct ctl_table *table, int write,
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+ void *buffer, size_t *lenp, loff_t *ppos);
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#endif
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--
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2.45.2
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