34d9172655
Introduce support for the Qualcomm IPQ50xx SoC. This series adds support for the following components: - minimal boot support: GCC/pinctrl/watchdog/CPUFreq/SDI (upstreamed) - USB2 (upstreamed) - Thermal/Tsens - PCIe gen2 1&2-lane PHY and controller - PWM and PWM LED - QPIC SPI NAND controller - CMN PLL Block (provider of fixed rate clocks to GCC/ethernet/more.) - Ethernet: IPQ5018 Internal GE PHY (1 gbps) - Remoteproc MPD driver for IPQ5018 (2.4G) & QCN6122 (5/6G) Wifi Co-developed-by: Ziyang Huang <hzyitc@outlook.com> Signed-off-by: Ziyang Huang <hzyitc@outlook.com> Signed-off-by: George Moussalem <george.moussalem@outlook.com> Link: https://github.com/openwrt/openwrt/pull/17182 Signed-off-by: Robert Marko <robimarko@gmail.com>
46 lines
1.2 KiB
Diff
46 lines
1.2 KiB
Diff
From 1b625a37b96b0448aac126d7720eec38de8e5956 Mon Sep 17 00:00:00 2001
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From: Ziyang Huang <hzyitc@outlook.com>
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Date: Sun, 8 Sep 2024 16:40:11 +0800
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Subject: [PATCH 2/2] arm64: dts: qcom: ipq5018: Add ethernet cmn node
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Signed-off-by: Ziyang Huang <hzyitc@outlook.com>
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---
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arch/arm64/boot/dts/qcom/ipq5018.dtsi | 19 +++++++++++++++++++
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1 file changed, 19 insertions(+)
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--- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
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+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
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@@ -16,6 +16,12 @@
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#size-cells = <2>;
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clocks {
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+ cmn_pll_ref_clk: cmn-pll-ref-clk {
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+ compatible = "fixed-clock";
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+ clock-frequency = <96000000>;
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+ #clock-cells = <0>;
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+ };
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+
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sleep_clk: sleep-clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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@@ -186,6 +192,19 @@
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status = "disabled";
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};
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+ cmn_pll: clock-controller@9b000 {
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+ compatible = "qcom,ipq9574-cmn-pll";
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+ reg = <0x0009b000 0x800>,
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+ <0x19475c4 0x4>;
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+ reg-names = "cmn",
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+ "tcsr";
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+ clocks = <&cmn_pll_ref_clk>,
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+ <&gcc GCC_CMN_BLK_AHB_CLK>,
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+ <&gcc GCC_CMN_BLK_SYS_CLK>;
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+ clock-names = "ref", "ahb", "sys";
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+ #clock-cells = <1>;
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+ };
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+
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qfprom: qfprom@a0000 {
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compatible = "qcom,ipq5018-qfprom", "qcom,qfprom";
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reg = <0xa0000 0x1000>;
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