34d9172655
Introduce support for the Qualcomm IPQ50xx SoC. This series adds support for the following components: - minimal boot support: GCC/pinctrl/watchdog/CPUFreq/SDI (upstreamed) - USB2 (upstreamed) - Thermal/Tsens - PCIe gen2 1&2-lane PHY and controller - PWM and PWM LED - QPIC SPI NAND controller - CMN PLL Block (provider of fixed rate clocks to GCC/ethernet/more.) - Ethernet: IPQ5018 Internal GE PHY (1 gbps) - Remoteproc MPD driver for IPQ5018 (2.4G) & QCN6122 (5/6G) Wifi Co-developed-by: Ziyang Huang <hzyitc@outlook.com> Signed-off-by: Ziyang Huang <hzyitc@outlook.com> Signed-off-by: George Moussalem <george.moussalem@outlook.com> Link: https://github.com/openwrt/openwrt/pull/17182 Signed-off-by: Robert Marko <robimarko@gmail.com>
79 lines
2.4 KiB
Diff
79 lines
2.4 KiB
Diff
From a28797563b8c97c9abced82e0cf89302fcd2bf37 Mon Sep 17 00:00:00 2001
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From: Ziyang Huang <hzyitc@outlook.com>
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Date: Sun, 8 Sep 2024 16:40:11 +0800
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Subject: [PATCH 1/2] clk: qcom: cmn-pll: add IPQ5018 support
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Add support for IPQ5018 (and removing dependency on the IPQ9574 platform).
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The common network block in IPQ5018 must be enabled first through a
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specific register at a fixed offset in the TCSR area, set in the DTS.
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Signed-off-by: Ziyang Huang <hzyitc@outlook.com>
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Signed-off-by: George Moussalem <george.moussalem@outlook.com>
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---
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drivers/clk/qcom/Kconfig | 1 -
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drivers/clk/qcom/clk-ipq-cmn-pll.c | 29 +++++++++++++++++++++++++++++
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2 files changed, 29 insertions(+), 1 deletion(-)
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--- a/drivers/clk/qcom/Kconfig
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+++ b/drivers/clk/qcom/Kconfig
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@@ -141,7 +141,6 @@ config IPQ_APSS_6018
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config IPQ_CMN_PLL
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tristate "IPQ CMN PLL Clock Controller"
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- depends on IPQ_GCC_9574
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help
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Support for CMN PLL clock controller on IPQ platform. The
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CMN PLL feeds the reference clocks to the Ethernet devices
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--- a/drivers/clk/qcom/clk-ipq-cmn-pll.c
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+++ b/drivers/clk/qcom/clk-ipq-cmn-pll.c
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@@ -42,6 +42,9 @@
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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+#define TCSR_ETH_CMN 0x0
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+#define TCSR_ETH_CMN_ENABLE BIT(0)
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+
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#define CMN_PLL_REFCLK_SRC_SELECTION 0x28
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#define CMN_PLL_REFCLK_SRC_DIV GENMASK(9, 8)
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@@ -79,6 +82,28 @@ static const struct cmn_pll_fixed_output
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CLK_PLL_OUTPUT(ETH_25MHZ_CLK, "eth-25mhz", 25000000UL),
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};
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+static int ipq_cmn_pll_tcsr_enable(struct platform_device *pdev)
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+{
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+ struct resource *res;
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+ void __iomem *tcsr_base;
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+ u32 val;
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+
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+ /* For IPQ50xx, tcsr is necessary to enable cmn block */
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+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "tcsr");
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+ if (!res)
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+ return 0;
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+
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+ tcsr_base = devm_ioremap_resource(&pdev->dev, res);
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+ if (IS_ERR_OR_NULL(tcsr_base))
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+ return PTR_ERR(tcsr_base);
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+
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+ val = readl(tcsr_base + TCSR_ETH_CMN);
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+ val |= TCSR_ETH_CMN_ENABLE;
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+ writel(val, (tcsr_base + TCSR_ETH_CMN));
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+
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+ return 0;
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+}
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+
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static int ipq_cmn_pll_config(struct device *dev, unsigned long parent_rate)
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{
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void __iomem *base;
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@@ -181,6 +206,10 @@ static int ipq_cmn_pll_clk_probe(struct
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struct clk *clk;
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int ret;
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+ ret = ipq_cmn_pll_tcsr_enable(pdev);
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+ if (ret)
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+ return dev_err_probe(dev, ret, "Enable CMN PLL failed\n");
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+
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/*
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* To access the CMN PLL registers, the GCC AHB & SYSY clocks
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* for CMN PLL block need to be enabled.
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