34d9172655
Introduce support for the Qualcomm IPQ50xx SoC. This series adds support for the following components: - minimal boot support: GCC/pinctrl/watchdog/CPUFreq/SDI (upstreamed) - USB2 (upstreamed) - Thermal/Tsens - PCIe gen2 1&2-lane PHY and controller - PWM and PWM LED - QPIC SPI NAND controller - CMN PLL Block (provider of fixed rate clocks to GCC/ethernet/more.) - Ethernet: IPQ5018 Internal GE PHY (1 gbps) - Remoteproc MPD driver for IPQ5018 (2.4G) & QCN6122 (5/6G) Wifi Co-developed-by: Ziyang Huang <hzyitc@outlook.com> Signed-off-by: Ziyang Huang <hzyitc@outlook.com> Signed-off-by: George Moussalem <george.moussalem@outlook.com> Link: https://github.com/openwrt/openwrt/pull/17182 Signed-off-by: Robert Marko <robimarko@gmail.com>
26 lines
882 B
Diff
26 lines
882 B
Diff
From 3d550dc3eb4eaa2fe1d0668ed67e835c91487d61 Mon Sep 17 00:00:00 2001
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From: Ziyang Huang <hzyitc@outlook.com>
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Date: Sun, 8 Sep 2024 16:40:11 +0800
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Subject: [PATCH 2/2] mtd: spinand: qpic only support max 4 bytes ID
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The QPIC SPI NAND controller supports a max of 4 bytes of device ID.
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As such, set a maximum of 4 bytes.
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Signed-off-by: Ziyang Huang <hzyitc@outlook.com>
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Signed-off-by: George Moussalem <george.moussalem@outlook.com>
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---
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drivers/mtd/nand/spi/core.c | 2 +-
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1 file changed, 1 insertion(+), 1 deletion(-)
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--- a/drivers/mtd/nand/spi/core.c
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+++ b/drivers/mtd/nand/spi/core.c
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@@ -1087,7 +1087,7 @@ int spinand_match_and_init(struct spinan
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if (rdid_method != info->devid.method)
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continue;
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- if (memcmp(id + 1, info->devid.id, info->devid.len))
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+ if (memcmp(id + 1, info->devid.id, min(3, info->devid.len)))
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continue;
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nand->memorg = table[i].memorg;
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