34d9172655
Introduce support for the Qualcomm IPQ50xx SoC. This series adds support for the following components: - minimal boot support: GCC/pinctrl/watchdog/CPUFreq/SDI (upstreamed) - USB2 (upstreamed) - Thermal/Tsens - PCIe gen2 1&2-lane PHY and controller - PWM and PWM LED - QPIC SPI NAND controller - CMN PLL Block (provider of fixed rate clocks to GCC/ethernet/more.) - Ethernet: IPQ5018 Internal GE PHY (1 gbps) - Remoteproc MPD driver for IPQ5018 (2.4G) & QCN6122 (5/6G) Wifi Co-developed-by: Ziyang Huang <hzyitc@outlook.com> Signed-off-by: Ziyang Huang <hzyitc@outlook.com> Signed-off-by: George Moussalem <george.moussalem@outlook.com> Link: https://github.com/openwrt/openwrt/pull/17182 Signed-off-by: Robert Marko <robimarko@gmail.com>
33 lines
936 B
Diff
33 lines
936 B
Diff
From: George Moussalem <george.moussalem@outlook.com>
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Subject: [PATCH] arm64: dts: qcom: ipq5018: Add QUP3 I2C node
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Date: Sun, 06 Oct 2024 16:34:11 +0400
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Add QUP3-I2C node.
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Signed-off-by: George Moussalem <george.moussalem@outlook.com>
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---
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--- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
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+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
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@@ -446,6 +446,21 @@
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status = "disabled";
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};
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+ blsp1_i2c3: i2c@78b7000 {
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+ compatible = "qcom,i2c-qup-v2.2.1";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ reg = <0x078b7000 0x600>;
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+ interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
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+ <&gcc GCC_BLSP1_AHB_CLK>;
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+ clock-names = "core", "iface";
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+ clock-frequency = <400000>;
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+ dmas = <&blsp_dma 9>, <&blsp_dma 8>;
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+ dma-names = "tx", "rx";
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+ status = "disabled";
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+ };
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+
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usb: usb@8af8800 {
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compatible = "qcom,ipq5018-dwc3", "qcom,dwc3";
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reg = <0x08af8800 0x400>;
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