34d9172655
Introduce support for the Qualcomm IPQ50xx SoC. This series adds support for the following components: - minimal boot support: GCC/pinctrl/watchdog/CPUFreq/SDI (upstreamed) - USB2 (upstreamed) - Thermal/Tsens - PCIe gen2 1&2-lane PHY and controller - PWM and PWM LED - QPIC SPI NAND controller - CMN PLL Block (provider of fixed rate clocks to GCC/ethernet/more.) - Ethernet: IPQ5018 Internal GE PHY (1 gbps) - Remoteproc MPD driver for IPQ5018 (2.4G) & QCN6122 (5/6G) Wifi Co-developed-by: Ziyang Huang <hzyitc@outlook.com> Signed-off-by: Ziyang Huang <hzyitc@outlook.com> Signed-off-by: George Moussalem <george.moussalem@outlook.com> Link: https://github.com/openwrt/openwrt/pull/17182 Signed-off-by: Robert Marko <robimarko@gmail.com>
28 lines
784 B
Diff
28 lines
784 B
Diff
From: George Moussalem <george.moussalem@outlook.com>
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Subject: [PATCH] arm64: dts: qcom: ipq5018: Add PWM node
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Date: Sun, 06 Oct 2024 16:34:11 +0400
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Add PWM node.
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Signed-off-by: George Moussalem <george.moussalem@outlook.com>
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---
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--- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
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+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
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@@ -343,6 +343,16 @@
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reg = <0x01937000 0x21000>;
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};
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+ pwm: pwm@1941010 {
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+ compatible = "qcom,ipq5018-pwm", "qcom,ipq6018-pwm";
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+ reg = <0x01941010 0x20>;
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+ clocks = <&gcc GCC_ADSS_PWM_CLK>;
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+ assigned-clocks = <&gcc GCC_ADSS_PWM_CLK>;
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+ assigned-clock-rates = <100000000>;
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+ #pwm-cells = <2>;
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+ status = "disabled";
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+ };
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+
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sdhc_1: mmc@7804000 {
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compatible = "qcom,ipq5018-sdhci", "qcom,sdhci-msm-v5";
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reg = <0x7804000 0x1000>;
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