34d9172655
Introduce support for the Qualcomm IPQ50xx SoC. This series adds support for the following components: - minimal boot support: GCC/pinctrl/watchdog/CPUFreq/SDI (upstreamed) - USB2 (upstreamed) - Thermal/Tsens - PCIe gen2 1&2-lane PHY and controller - PWM and PWM LED - QPIC SPI NAND controller - CMN PLL Block (provider of fixed rate clocks to GCC/ethernet/more.) - Ethernet: IPQ5018 Internal GE PHY (1 gbps) - Remoteproc MPD driver for IPQ5018 (2.4G) & QCN6122 (5/6G) Wifi Co-developed-by: Ziyang Huang <hzyitc@outlook.com> Signed-off-by: Ziyang Huang <hzyitc@outlook.com> Signed-off-by: George Moussalem <george.moussalem@outlook.com> Link: https://github.com/openwrt/openwrt/pull/17182 Signed-off-by: Robert Marko <robimarko@gmail.com>
78 lines
2.0 KiB
Diff
78 lines
2.0 KiB
Diff
From: George Moussalem <george.moussalem@outlook.com>
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Date: Tue, 07 Jan 2025 17:34:13 +0400
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Subject: [PATCH] phy: qualcomm: qcom-uniphy-pcie 28lp add support for IPQ5018
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The Qualcomm UNIPHY PCIe PHY 28lp is found on both IPQ5332 and IPQ5018.
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Adding the PHY init sequence, pipe clock rate, and compatible for IPQ5018.
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Signed-off-by: George Moussalem <george.moussalem@outlook.com>
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---
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--- a/drivers/phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c
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+++ b/drivers/phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c
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@@ -76,6 +76,40 @@ struct qcom_uniphy_pcie {
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#define phy_to_dw_phy(x) container_of((x), struct qca_uni_pcie_phy, phy)
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+static const struct qcom_uniphy_pcie_regs ipq5018_regs[] = {
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+ {
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+ .offset = SSCG_CTRL_REG_4,
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+ .val = 0x1cb9,
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+ }, {
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+ .offset = SSCG_CTRL_REG_5,
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+ .val = 0x023a,
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+ }, {
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+ .offset = SSCG_CTRL_REG_3,
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+ .val = 0xd360,
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+ }, {
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+ .offset = SSCG_CTRL_REG_1,
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+ .val = 0x1,
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+ }, {
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+ .offset = SSCG_CTRL_REG_2,
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+ .val = 0xeb,
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+ }, {
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+ .offset = CDR_CTRL_REG_4,
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+ .val = 0x3f9,
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+ }, {
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+ .offset = CDR_CTRL_REG_5,
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+ .val = 0x1c9,
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+ }, {
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+ .offset = CDR_CTRL_REG_2,
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+ .val = 0x419,
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+ }, {
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+ .offset = CDR_CTRL_REG_1,
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+ .val = 0x200,
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+ }, {
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+ .offset = PCS_INTERNAL_CONTROL_2,
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+ .val = 0xf101,
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+ },
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+};
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+
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static const struct qcom_uniphy_pcie_regs ipq5332_regs[] = {
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{
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.offset = PHY_CFG_PLLCFG,
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@@ -89,6 +123,14 @@ static const struct qcom_uniphy_pcie_reg
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},
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};
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+static const struct qcom_uniphy_pcie_data ipq5018_data = {
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+ .lane_offset = 0x800,
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+ .phy_type = PHY_TYPE_PCIE_GEN2,
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+ .init_seq = ipq5018_regs,
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+ .init_seq_num = ARRAY_SIZE(ipq5018_regs),
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+ .pipe_clk_rate = 125000000,
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+};
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+
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static const struct qcom_uniphy_pcie_data ipq5332_data = {
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.lane_offset = 0x800,
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.phy_type = PHY_TYPE_PCIE_GEN3,
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@@ -212,6 +254,9 @@ static inline int phy_pipe_clk_register(
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static const struct of_device_id qcom_uniphy_pcie_id_table[] = {
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{
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+ .compatible = "qcom,ipq5018-uniphy-pcie-phy",
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+ .data = &ipq5018_data,
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+ }, {
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.compatible = "qcom,ipq5332-uniphy-pcie-phy",
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.data = &ipq5332_data,
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}, {
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