34d9172655
Introduce support for the Qualcomm IPQ50xx SoC. This series adds support for the following components: - minimal boot support: GCC/pinctrl/watchdog/CPUFreq/SDI (upstreamed) - USB2 (upstreamed) - Thermal/Tsens - PCIe gen2 1&2-lane PHY and controller - PWM and PWM LED - QPIC SPI NAND controller - CMN PLL Block (provider of fixed rate clocks to GCC/ethernet/more.) - Ethernet: IPQ5018 Internal GE PHY (1 gbps) - Remoteproc MPD driver for IPQ5018 (2.4G) & QCN6122 (5/6G) Wifi Co-developed-by: Ziyang Huang <hzyitc@outlook.com> Signed-off-by: Ziyang Huang <hzyitc@outlook.com> Signed-off-by: George Moussalem <george.moussalem@outlook.com> Link: https://github.com/openwrt/openwrt/pull/17182 Signed-off-by: Robert Marko <robimarko@gmail.com>
63 lines
2.2 KiB
Diff
63 lines
2.2 KiB
Diff
From 50492f929486c044b43cb3e2c0e040aa9b61ea2b Mon Sep 17 00:00:00 2001
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From: Gokul Sriram Palanisamy <quic_gokulsri@quicinc.com>
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Date: Mon, 25 Sep 2023 15:58:25 +0530
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Subject: [PATCH] clk: qcom: apss-ipq-pll: add support for IPQ5018
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IPQ5018 APSS PLL is of type Stromer. Reuse Stromer Plus PLL offsets,
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add configuration values and the compatible.
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Co-developed-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
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Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
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Signed-off-by: Gokul Sriram Palanisamy <quic_gokulsri@quicinc.com>
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Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
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Link: https://lore.kernel.org/r/20230925102826.405446-3-quic_gokulsri@quicinc.com
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Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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---
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drivers/clk/qcom/apss-ipq-pll.c | 21 +++++++++++++++++++++
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1 file changed, 21 insertions(+)
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--- a/drivers/clk/qcom/apss-ipq-pll.c
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+++ b/drivers/clk/qcom/apss-ipq-pll.c
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@@ -73,6 +73,20 @@ static struct clk_alpha_pll ipq_pll_stro
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},
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};
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+static const struct alpha_pll_config ipq5018_pll_config = {
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+ .l = 0x32,
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+ .config_ctl_val = 0x4001075b,
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+ .config_ctl_hi_val = 0x304,
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+ .main_output_mask = BIT(0),
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+ .aux_output_mask = BIT(1),
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+ .early_output_mask = BIT(3),
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+ .alpha_en_mask = BIT(24),
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+ .status_val = 0x3,
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+ .status_mask = GENMASK(10, 8),
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+ .lock_det = BIT(2),
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+ .test_ctl_hi_val = 0x00400003,
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+};
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+
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static const struct alpha_pll_config ipq5332_pll_config = {
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.l = 0x2d,
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.config_ctl_val = 0x4001075b,
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@@ -129,6 +143,12 @@ struct apss_pll_data {
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const struct alpha_pll_config *pll_config;
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};
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+static const struct apss_pll_data ipq5018_pll_data = {
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+ .pll_type = CLK_ALPHA_PLL_TYPE_STROMER_PLUS,
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+ .pll = &ipq_pll_stromer_plus,
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+ .pll_config = &ipq5018_pll_config,
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+};
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+
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static struct apss_pll_data ipq5332_pll_data = {
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.pll_type = CLK_ALPHA_PLL_TYPE_STROMER_PLUS,
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.pll = &ipq_pll_stromer_plus,
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@@ -195,6 +215,7 @@ static int apss_ipq_pll_probe(struct pla
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}
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static const struct of_device_id apss_ipq_pll_match_table[] = {
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+ { .compatible = "qcom,ipq5018-a53pll", .data = &ipq5018_pll_data },
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{ .compatible = "qcom,ipq5332-a53pll", .data = &ipq5332_pll_data },
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{ .compatible = "qcom,ipq6018-a53pll", .data = &ipq6018_pll_data },
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{ .compatible = "qcom,ipq8074-a53pll", .data = &ipq8074_pll_data },
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