34d9172655
Introduce support for the Qualcomm IPQ50xx SoC. This series adds support for the following components: - minimal boot support: GCC/pinctrl/watchdog/CPUFreq/SDI (upstreamed) - USB2 (upstreamed) - Thermal/Tsens - PCIe gen2 1&2-lane PHY and controller - PWM and PWM LED - QPIC SPI NAND controller - CMN PLL Block (provider of fixed rate clocks to GCC/ethernet/more.) - Ethernet: IPQ5018 Internal GE PHY (1 gbps) - Remoteproc MPD driver for IPQ5018 (2.4G) & QCN6122 (5/6G) Wifi Co-developed-by: Ziyang Huang <hzyitc@outlook.com> Signed-off-by: Ziyang Huang <hzyitc@outlook.com> Signed-off-by: George Moussalem <george.moussalem@outlook.com> Link: https://github.com/openwrt/openwrt/pull/17182 Signed-off-by: Robert Marko <robimarko@gmail.com>
57 lines
1.8 KiB
Diff
57 lines
1.8 KiB
Diff
From a1f42e08f0f04b72a6597f080db4bfbb3737910c Mon Sep 17 00:00:00 2001
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From: Robert Marko <robimarko@gmail.com>
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Date: Wed, 4 Oct 2023 21:12:30 +0200
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Subject: [PATCH] arm64: dts: qcom: ipq5018: add QUP1 SPI controller
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Add the required BAM and QUP nodes for the QUP1 SPI controller on IPQ5018.
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Signed-off-by: Robert Marko <robimarko@gmail.com>
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Reviewed-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
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Link: https://lore.kernel.org/r/20231004191303.331055-1-robimarko@gmail.com
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[bjorn: Padded address to 8 digits, fixed node sort order]
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Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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---
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arch/arm64/boot/dts/qcom/ipq5018.dtsi | 24 ++++++++++++++++++++++++
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1 file changed, 24 insertions(+)
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--- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
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+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
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@@ -159,6 +159,16 @@
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status = "disabled";
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};
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+ blsp_dma: dma-controller@7884000 {
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+ compatible = "qcom,bam-v1.7.0";
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+ reg = <0x07884000 0x1d000>;
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+ interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&gcc GCC_BLSP1_AHB_CLK>;
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+ clock-names = "bam_clk";
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+ #dma-cells = <1>;
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+ qcom,ee = <0>;
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+ };
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+
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blsp1_uart1: serial@78af000 {
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compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
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reg = <0x078af000 0x200>;
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@@ -169,6 +179,20 @@
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status = "disabled";
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};
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+ blsp1_spi1: spi@78b5000 {
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+ compatible = "qcom,spi-qup-v2.2.1";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ reg = <0x078b5000 0x600>;
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+ interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
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+ <&gcc GCC_BLSP1_AHB_CLK>;
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+ clock-names = "core", "iface";
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+ dmas = <&blsp_dma 4>, <&blsp_dma 5>;
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+ dma-names = "tx", "rx";
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+ status = "disabled";
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+ };
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+
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usb: usb@8af8800 {
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compatible = "qcom,ipq5018-dwc3", "qcom,dwc3";
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reg = <0x08af8800 0x400>;
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