251f76c1c6
Adds latest 6.6 patches from the Raspberry Pi repository. These patches were generated from: https://github.com/raspberrypi/linux/commits/rpi-6.6.y/ With the following command: git format-patch -N v6.6.83..HEAD (HEAD -> 08d4e8f52256bd422d8a1f876411603f627d0a82) Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
199 lines
6.9 KiB
Diff
199 lines
6.9 KiB
Diff
From 85e1a7592aa192d760159f9bc6e83d56fdf433f3 Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?Ma=C3=ADra=20Canal?= <mcanal@igalia.com>
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Date: Sat, 22 Feb 2025 15:49:49 -0300
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Subject: [PATCH] drm/v3d: Use V3D_SMS registers for power on/off and reset on
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V3D 7.x
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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In addition to the standard reset controller, V3D 7.x requires configuring
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the V3D_SMS registers for proper power on/off and reset. Add the new
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registers to `v3d_regs.h` and ensure they are properly configured during
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device probing, removal, and reset.
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This change fixes GPU reset issues on the Raspberry Pi 5 (BCM2712).
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Without exposing these registers, a GPU reset causes the GPU to hang,
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stopping any further job execution and freezing the desktop GUI. The same
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issue occurs when unloading and loading the v3d driver.
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Link: https://github.com/raspberrypi/linux/issues/6660
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Signed-off-by: Maíra Canal <mcanal@igalia.com>
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---
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drivers/gpu/drm/v3d/v3d_drv.c | 40 ++++++++++++++++++++++++++++++++++
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drivers/gpu/drm/v3d/v3d_drv.h | 11 ++++++++++
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drivers/gpu/drm/v3d/v3d_gem.c | 17 +++++++++++++++
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drivers/gpu/drm/v3d/v3d_regs.h | 26 ++++++++++++++++++++++
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4 files changed, 94 insertions(+)
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--- a/drivers/gpu/drm/v3d/v3d_drv.c
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+++ b/drivers/gpu/drm/v3d/v3d_drv.c
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@@ -198,6 +198,36 @@ static const struct of_device_id v3d_of_
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};
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MODULE_DEVICE_TABLE(of, v3d_of_match);
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+static void
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+v3d_idle_sms(struct v3d_dev *v3d)
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+{
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+ if (v3d->ver < V3D_GEN_71)
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+ return;
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+
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+ V3D_SMS_WRITE(V3D_SMS_TEE_CS, V3D_SMS_CLEAR_POWER_OFF);
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+
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+ if (wait_for((V3D_GET_FIELD(V3D_SMS_READ(V3D_SMS_TEE_CS),
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+ V3D_SMS_STATE) == V3D_SMS_IDLE), 100)) {
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+ DRM_ERROR("Failed to power up SMS\n");
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+ }
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+
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+ v3d_reset_sms(v3d);
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+}
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+
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+static void
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+v3d_power_off_sms(struct v3d_dev *v3d)
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+{
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+ if (v3d->ver < V3D_GEN_71)
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+ return;
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+
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+ V3D_SMS_WRITE(V3D_SMS_TEE_CS, V3D_SMS_POWER_OFF);
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+
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+ if (wait_for((V3D_GET_FIELD(V3D_SMS_READ(V3D_SMS_TEE_CS),
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+ V3D_SMS_STATE) == V3D_SMS_POWER_OFF_STATE), 100)) {
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+ DRM_ERROR("Failed to power off SMS\n");
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+ }
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+}
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+
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static int
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map_regs(struct v3d_dev *v3d, void __iomem **regs, const char *name)
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{
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@@ -237,6 +267,12 @@ static int v3d_platform_drm_probe(struct
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if (ret)
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return ret;
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+ if (v3d->ver >= V3D_GEN_71) {
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+ ret = map_regs(v3d, &v3d->sms_regs, "sms");
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+ if (ret)
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+ return ret;
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+ }
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+
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v3d->clk = devm_clk_get_optional(dev, NULL);
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if (IS_ERR(v3d->clk))
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return dev_err_probe(dev, PTR_ERR(v3d->clk), "Failed to get V3D clock\n");
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@@ -247,6 +283,8 @@ static int v3d_platform_drm_probe(struct
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return ret;
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}
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+ v3d_idle_sms(v3d);
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+
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mmu_debug = V3D_READ(V3D_MMU_DEBUG_INFO);
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mask = DMA_BIT_MASK(30 + V3D_GET_FIELD(mmu_debug, V3D_MMU_PA_WIDTH));
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ret = dma_set_mask_and_coherent(dev, mask);
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@@ -361,6 +399,8 @@ static void v3d_platform_drm_remove(stru
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dma_free_wc(v3d->drm.dev, 4096, v3d->mmu_scratch,
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v3d->mmu_scratch_paddr);
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+ v3d_power_off_sms(v3d);
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+
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clk_disable_unprepare(v3d->clk);
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}
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--- a/drivers/gpu/drm/v3d/v3d_drv.h
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+++ b/drivers/gpu/drm/v3d/v3d_drv.h
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@@ -135,6 +135,7 @@ struct v3d_dev {
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void __iomem *core_regs[3];
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void __iomem *bridge_regs;
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void __iomem *gca_regs;
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+ void __iomem *sms_regs;
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struct clk *clk;
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struct delayed_work clk_down_work;
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unsigned long clk_up_rate, clk_down_rate;
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@@ -277,6 +278,15 @@ to_v3d_fence(struct dma_fence *fence)
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#define V3D_GCA_READ(offset) readl(v3d->gca_regs + offset)
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#define V3D_GCA_WRITE(offset, val) writel(val, v3d->gca_regs + offset)
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+#define V3D_SMS_IDLE 0x0
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+#define V3D_SMS_ISOLATING_FOR_RESET 0xa
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+#define V3D_SMS_RESETTING 0xb
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+#define V3D_SMS_ISOLATING_FOR_POWER_OFF 0xc
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+#define V3D_SMS_POWER_OFF_STATE 0xd
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+
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+#define V3D_SMS_READ(offset) readl(v3d->sms_regs + (offset))
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+#define V3D_SMS_WRITE(offset, val) writel(val, v3d->sms_regs + (offset))
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+
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#define V3D_CORE_READ(core, offset) readl(v3d->core_regs[core] + offset)
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#define V3D_CORE_WRITE(core, offset, val) writel(val, v3d->core_regs[core] + offset)
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@@ -455,6 +465,7 @@ int v3d_wait_bo_ioctl(struct drm_device
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struct drm_file *file_priv);
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void v3d_job_cleanup(struct v3d_job *job);
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void v3d_job_put(struct v3d_job *job);
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+void v3d_reset_sms(struct v3d_dev *v3d);
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void v3d_reset(struct v3d_dev *v3d);
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void v3d_invalidate_caches(struct v3d_dev *v3d);
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void v3d_clean_caches(struct v3d_dev *v3d);
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--- a/drivers/gpu/drm/v3d/v3d_gem.c
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+++ b/drivers/gpu/drm/v3d/v3d_gem.c
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@@ -152,6 +152,22 @@ v3d_reset_v3d(struct v3d_dev *v3d)
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}
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void
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+v3d_reset_sms(struct v3d_dev *v3d)
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+{
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+ if (v3d->ver < V3D_GEN_71)
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+ return;
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+
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+ V3D_SMS_WRITE(V3D_SMS_REE_CS, V3D_SET_FIELD(0x4, V3D_SMS_STATE));
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+
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+ if (wait_for(!(V3D_GET_FIELD(V3D_SMS_READ(V3D_SMS_REE_CS),
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+ V3D_SMS_STATE) == V3D_SMS_ISOLATING_FOR_RESET) &&
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+ !(V3D_GET_FIELD(V3D_SMS_READ(V3D_SMS_REE_CS),
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+ V3D_SMS_STATE) == V3D_SMS_RESETTING), 100)) {
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+ DRM_ERROR("Failed to wait for SMS reset\n");
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+ }
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+}
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+
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+void
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v3d_reset(struct v3d_dev *v3d)
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{
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struct drm_device *dev = &v3d->drm;
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@@ -166,6 +182,7 @@ v3d_reset(struct v3d_dev *v3d)
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v3d_idle_axi(v3d, 0);
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v3d_idle_gca(v3d);
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+ v3d_reset_sms(v3d);
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v3d_reset_v3d(v3d);
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v3d_mmu_set_page_table(v3d);
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--- a/drivers/gpu/drm/v3d/v3d_regs.h
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+++ b/drivers/gpu/drm/v3d/v3d_regs.h
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@@ -543,4 +543,30 @@
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# define V3D_ERR_VPAERGS BIT(1)
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# define V3D_ERR_VPAEABB BIT(0)
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+#define V3D_SMS_REE_CS 0x00000
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+#define V3D_SMS_TEE_CS 0x00400
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+# define V3D_SMS_INTERRUPT BIT(31)
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+# define V3D_SMS_POWER_OFF BIT(30)
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+# define V3D_SMS_CLEAR_POWER_OFF BIT(29)
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+# define V3D_SMS_LOCK BIT(28)
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+# define V3D_SMS_CLEAR_LOCK BIT(27)
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+# define V3D_SMS_SVP_MODE_EXIT BIT(26)
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+# define V3D_SMS_CLEAR_SVP_MODE_EXIT BIT(25)
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+# define V3D_SMS_SVP_MODE_ENTER BIT(24)
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+# define V3D_SMS_CLEAR_SVP_MODE_ENTER BIT(23)
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+# define V3D_SMS_THEIR_MODE_EXIT BIT(22)
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+# define V3D_SMS_THEIR_MODE_ENTER BIT(21)
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+# define V3D_SMS_OUR_MODE_EXIT BIT(20)
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+# define V3D_SMS_CLEAR_OUR_MODE_EXIT BIT(19)
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+# define V3D_SMS_SEQ_PC_MASK V3D_MASK(16, 10)
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+# define V3D_SMS_SEQ_PC_SHIFT 10
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+# define V3D_SMS_HUBCORE_STATUS_MASK V3D_MASK(9, 8)
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+# define V3D_SMS_HUBCORE_STATUS_SHIFT 8
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+# define V3D_SMS_NEW_MODE_MASK V3D_MASK(7, 6)
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+# define V3D_SMS_NEW_MODE_SHIFT 6
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+# define V3D_SMS_OLD_MODE_MASK V3D_MASK(5, 4)
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+# define V3D_SMS_OLD_MODE_SHIFT 4
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+# define V3D_SMS_STATE_MASK V3D_MASK(3, 0)
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+# define V3D_SMS_STATE_SHIFT 0
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+
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#endif /* V3D_REGS_H */
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