251f76c1c6
Adds latest 6.6 patches from the Raspberry Pi repository. These patches were generated from: https://github.com/raspberrypi/linux/commits/rpi-6.6.y/ With the following command: git format-patch -N v6.6.83..HEAD (HEAD -> 08d4e8f52256bd422d8a1f876411603f627d0a82) Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
326 lines
11 KiB
Diff
326 lines
11 KiB
Diff
From ba9883e3b667e4f1fbeacc4346f6e9179a3a5479 Mon Sep 17 00:00:00 2001
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From: Nick Hollinghurst <nick.hollinghurst@raspberrypi.com>
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Date: Mon, 20 Jan 2025 11:20:48 +0000
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Subject: [PATCH] drm: rp1: rp1-dpi: Add "rgb_order" property (to match VC4
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DPI)
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As on VC4, the OF property overrides the order implied by media
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bus format. Only 4 of the 6 possible orders are supported. New
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add-on hardware designs should not rely on this "legacy" feature.
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Signed-off-by: Nick Hollinghurst <nick.hollinghurst@raspberrypi.com>
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---
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drivers/gpu/drm/rp1/rp1-dpi/rp1_dpi.c | 15 ++
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drivers/gpu/drm/rp1/rp1-dpi/rp1_dpi.h | 8 +
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drivers/gpu/drm/rp1/rp1-dpi/rp1_dpi_hw.c | 191 ++++++++++++++---------
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3 files changed, 143 insertions(+), 71 deletions(-)
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--- a/drivers/gpu/drm/rp1/rp1-dpi/rp1_dpi.c
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+++ b/drivers/gpu/drm/rp1/rp1-dpi/rp1_dpi.c
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@@ -292,6 +292,7 @@ static int rp1dpi_platform_probe(struct
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struct device *dev = &pdev->dev;
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struct rp1_dpi *dpi;
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struct drm_bridge *bridge = NULL;
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+ const char *rgb_order = NULL;
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struct drm_panel *panel;
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int i, j, ret;
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@@ -353,6 +354,20 @@ static int rp1dpi_platform_probe(struct
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if (ret)
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goto done_err;
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+ dpi->rgb_order_override = RP1DPI_ORDER_UNCHANGED;
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+ if (!of_property_read_string(dev->of_node, "rgb_order", &rgb_order)) {
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+ if (!strcmp(rgb_order, "rgb"))
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+ dpi->rgb_order_override = RP1DPI_ORDER_RGB;
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+ else if (!strcmp(rgb_order, "bgr"))
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+ dpi->rgb_order_override = RP1DPI_ORDER_BGR;
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+ else if (!strcmp(rgb_order, "grb"))
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+ dpi->rgb_order_override = RP1DPI_ORDER_GRB;
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+ else if (!strcmp(rgb_order, "brg"))
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+ dpi->rgb_order_override = RP1DPI_ORDER_BRG;
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+ else
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+ DRM_ERROR("Invalid dpi order %s - ignored\n", rgb_order);
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+ }
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+
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/* Check if PIO can snoop on or override DPI's GPIO1 */
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dpi->gpio1_used = false;
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for (i = 0; !dpi->gpio1_used; i++) {
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--- a/drivers/gpu/drm/rp1/rp1-dpi/rp1_dpi.h
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+++ b/drivers/gpu/drm/rp1/rp1-dpi/rp1_dpi.h
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@@ -25,6 +25,13 @@
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#define RP1DPI_CLK_PLLCORE 2
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#define RP1DPI_NUM_CLOCKS 3
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+/* Codes (in LE byte order) used for S/W permutation */
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+#define RP1DPI_ORDER_UNCHANGED 0
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+#define RP1DPI_ORDER_RGB 0x020100
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+#define RP1DPI_ORDER_BGR 0x000102
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+#define RP1DPI_ORDER_GRB 0x020001
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+#define RP1DPI_ORDER_BRG 0x010002
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+
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/* ---------------------------------------------------------------------- */
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struct rp1_dpi {
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@@ -45,6 +52,7 @@ struct rp1_dpi {
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u32 bus_fmt;
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bool de_inv, clk_inv;
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bool dpi_running, pipe_enabled;
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+ unsigned int rgb_order_override;
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struct completion finished;
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/* Experimental stuff for interlace follows */
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--- a/drivers/gpu/drm/rp1/rp1-dpi/rp1_dpi_hw.c
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+++ b/drivers/gpu/drm/rp1/rp1-dpi/rp1_dpi_hw.c
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@@ -223,12 +223,90 @@ int rp1dpi_hw_busy(struct rp1_dpi *dpi)
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return (rp1dpi_hw_read(dpi, DPI_DMA_STATUS) & 0xF8F) ? 1 : 0;
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}
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-/* Table of supported input (in-memory/DMA) pixel formats. */
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+/*
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+ * Table of supported input (in-memory/DMA) pixel formats.
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+ *
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+ * RP1 DPI describes RGB components in terms of their MS bit position, a 10-bit
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+ * left-aligned bit-mask, and an optional right-shift-and-OR used for scaling.
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+ * To make it easier to permute R, G and B components, we re-pack these fields
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+ * into 32-bit code-words, which don't themselves correspond to any register.
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+ */
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+
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+#define RGB_CODE(scale, shift, mask) (((scale) << 24) | ((shift) << 16) | (mask))
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+#define RGB_SCALE(c) ((c) >> 24)
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+#define RGB_SHIFT(c) (((c) >> 16) & 31)
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+#define RGB_MASK(c) ((c) & 0x3ff)
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+
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struct rp1dpi_ipixfmt {
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- u32 format; /* DRM format code */
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- u32 mask; /* RGB masks (10 bits each, left justified) */
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- u32 shift; /* RGB MSB positions in the memory word */
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- u32 rgbsz; /* Shifts used for scaling; also (BPP/8-1) */
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+ u32 format; /* DRM format code */
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+ u32 rgb_code[3]; /* (width&7), MS bit position, 10-bit mask */
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+ u32 bpp; /* Bytes per pixel minus one */
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+};
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+
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+static const struct rp1dpi_ipixfmt my_formats[] = {
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+ {
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+ .format = DRM_FORMAT_XRGB8888,
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+ .rgb_code = {
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+ RGB_CODE(0, 23, 0x3fc),
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+ RGB_CODE(0, 15, 0x3fc),
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+ RGB_CODE(0, 7, 0x3fc),
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+ },
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+ .bpp = 3,
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+ },
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+ {
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+ .format = DRM_FORMAT_XBGR8888,
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+ .rgb_code = {
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+ RGB_CODE(0, 7, 0x3fc),
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+ RGB_CODE(0, 15, 0x3fc),
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+ RGB_CODE(0, 23, 0x3fc),
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+ },
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+ .bpp = 3,
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+ },
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+ {
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+ .format = DRM_FORMAT_ARGB8888,
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+ .rgb_code = {
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+ RGB_CODE(0, 23, 0x3fc),
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+ RGB_CODE(0, 15, 0x3fc),
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+ RGB_CODE(0, 7, 0x3fc),
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+ },
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+ .bpp = 3,
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+ },
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+ {
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+ .format = DRM_FORMAT_ABGR8888,
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+ .rgb_code = {
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+ RGB_CODE(0, 7, 0x3fc),
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+ RGB_CODE(0, 15, 0x3fc),
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+ RGB_CODE(0, 23, 0x3fc),
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+ },
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+ .bpp = 3,
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+ },
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+ {
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+ .format = DRM_FORMAT_RGB888,
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+ .rgb_code = {
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+ RGB_CODE(0, 23, 0x3fc),
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+ RGB_CODE(0, 15, 0x3fc),
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+ RGB_CODE(0, 7, 0x3fc),
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+ },
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+ .bpp = 2,
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+ },
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+ {
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+ .format = DRM_FORMAT_BGR888,
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+ .rgb_code = {
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+ RGB_CODE(0, 7, 0x3fc),
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+ RGB_CODE(0, 15, 0x3fc),
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+ RGB_CODE(0, 23, 0x3fc),
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+ },
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+ .bpp = 2,
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+ },
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+ {
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+ .format = DRM_FORMAT_RGB565,
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+ .rgb_code = {
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+ RGB_CODE(5, 15, 0x3e0),
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+ RGB_CODE(6, 10, 0x3f0),
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+ RGB_CODE(5, 4, 0x3e0),
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+ },
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+ .bpp = 1,
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+ },
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};
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#define IMASK_RGB(r, g, b) (FIELD_PREP_CONST(DPI_DMA_IMASK_R_MASK, r) | \
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@@ -244,63 +322,13 @@ struct rp1dpi_ipixfmt {
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FIELD_PREP_CONST(DPI_DMA_SHIFT_OG_MASK, g) | \
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FIELD_PREP_CONST(DPI_DMA_SHIFT_OB_MASK, b))
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-static const struct rp1dpi_ipixfmt my_formats[] = {
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- {
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- .format = DRM_FORMAT_XRGB8888,
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- .mask = IMASK_RGB(0x3fc, 0x3fc, 0x3fc),
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- .shift = ISHIFT_RGB(23, 15, 7),
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- .rgbsz = FIELD_PREP_CONST(DPI_DMA_RGBSZ_BPP_MASK, 3),
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- },
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- {
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- .format = DRM_FORMAT_XBGR8888,
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- .mask = IMASK_RGB(0x3fc, 0x3fc, 0x3fc),
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- .shift = ISHIFT_RGB(7, 15, 23),
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- .rgbsz = FIELD_PREP_CONST(DPI_DMA_RGBSZ_BPP_MASK, 3),
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- },
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- {
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- .format = DRM_FORMAT_ARGB8888,
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- .mask = IMASK_RGB(0x3fc, 0x3fc, 0x3fc),
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- .shift = ISHIFT_RGB(23, 15, 7),
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- .rgbsz = FIELD_PREP_CONST(DPI_DMA_RGBSZ_BPP_MASK, 3),
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- },
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- {
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- .format = DRM_FORMAT_ABGR8888,
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- .mask = IMASK_RGB(0x3fc, 0x3fc, 0x3fc),
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- .shift = ISHIFT_RGB(7, 15, 23),
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- .rgbsz = FIELD_PREP_CONST(DPI_DMA_RGBSZ_BPP_MASK, 3),
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- },
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- {
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- .format = DRM_FORMAT_RGB888,
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- .mask = IMASK_RGB(0x3fc, 0x3fc, 0x3fc),
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- .shift = ISHIFT_RGB(23, 15, 7),
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- .rgbsz = FIELD_PREP_CONST(DPI_DMA_RGBSZ_BPP_MASK, 2),
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- },
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- {
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- .format = DRM_FORMAT_BGR888,
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- .mask = IMASK_RGB(0x3fc, 0x3fc, 0x3fc),
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- .shift = ISHIFT_RGB(7, 15, 23),
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- .rgbsz = FIELD_PREP_CONST(DPI_DMA_RGBSZ_BPP_MASK, 2),
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- },
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- {
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- .format = DRM_FORMAT_RGB565,
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- .mask = IMASK_RGB(0x3e0, 0x3f0, 0x3e0),
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- .shift = ISHIFT_RGB(15, 10, 4),
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- .rgbsz = (FIELD_PREP_CONST(DPI_DMA_RGBSZ_R_MASK, 5) |
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- FIELD_PREP_CONST(DPI_DMA_RGBSZ_G_MASK, 6) |
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- FIELD_PREP_CONST(DPI_DMA_RGBSZ_B_MASK, 5) |
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- FIELD_PREP_CONST(DPI_DMA_RGBSZ_BPP_MASK, 1)),
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- },
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- {
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- .format = DRM_FORMAT_BGR565,
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- .mask = IMASK_RGB(0x3e0, 0x3f0, 0x3e0),
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- .shift = ISHIFT_RGB(4, 10, 15),
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- .rgbsz = (FIELD_PREP_CONST(DPI_DMA_RGBSZ_R_MASK, 5) |
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- FIELD_PREP_CONST(DPI_DMA_RGBSZ_G_MASK, 6) |
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- FIELD_PREP_CONST(DPI_DMA_RGBSZ_B_MASK, 5) |
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- FIELD_PREP_CONST(DPI_DMA_RGBSZ_BPP_MASK, 1)),
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- }
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-};
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-
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+/*
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+ * Function to update *shift with output positions, and return output RGB masks.
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+ * By the time we get here, RGB order has been normalized to RGB (R most significant).
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+ * Note that an internal bus is 30 bits wide: bits [21:20], [11:10], [1:0] are dropped.
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+ * This makes the packed RGB5656 and RGB666 formats problematic, as colour components
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+ * need to straddle the gaps; we mitigate this by hijacking input masks and scaling.
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+ */
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static u32 set_output_format(u32 bus_format, u32 *shift, u32 *imask, u32 *rgbsz)
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{
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switch (bus_format) {
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@@ -308,6 +336,7 @@ static u32 set_output_format(u32 bus_for
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if (*shift == ISHIFT_RGB(15, 10, 4)) {
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/* When framebuffer is RGB565, we can output RGB565 */
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*shift = ISHIFT_RGB(15, 7, 0) | OSHIFT_RGB(19, 9, 0);
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+ *imask = IMASK_RGB(0x3fc, 0x3fc, 0);
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*rgbsz &= DPI_DMA_RGBSZ_BPP_MASK;
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return OMASK_RGB(0x3fc, 0x3fc, 0);
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}
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@@ -322,7 +351,7 @@ static u32 set_output_format(u32 bus_for
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case MEDIA_BUS_FMT_BGR666_1X18:
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/* due to a HW limitation, bit-depth is effectively RGB444 */
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*shift |= OSHIFT_RGB(23, 15, 7);
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- *imask &= IMASK_RGB(0x3c0, 0x3c0, 0x3c0);
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+ *imask = IMASK_RGB(0x3c0, 0x3c0, 0x3c0);
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*rgbsz = BITS(DPI_DMA_RGBSZ_R, 2) | (*rgbsz & DPI_DMA_RGBSZ_BPP_MASK);
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return OMASK_RGB(0x330, 0x3c0, 0x3c0);
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@@ -359,7 +388,8 @@ void rp1dpi_hw_setup(struct rp1_dpi *dpi
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struct drm_display_mode const *mode)
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{
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u32 shift, imask, omask, rgbsz, vctrl;
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- int i;
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+ u32 rgb_code[3];
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+ int order, i;
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drm_info(&dpi->drm,
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"in_fmt=\'%c%c%c%c\' bus_fmt=0x%x mode=%dx%d total=%dx%d%s %dkHz %cH%cV%cD%cC",
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@@ -373,26 +403,45 @@ void rp1dpi_hw_setup(struct rp1_dpi *dpi
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de_inv ? '-' : '+',
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dpi->clk_inv ? '-' : '+');
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- /*
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- * Configure all DPI/DMA block registers, except base address.
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- * DMA will not actually start until a FB base address is specified
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- * using rp1dpi_hw_update().
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- */
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+ /* Look up the input (in-memory) pixel format */
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for (i = 0; i < ARRAY_SIZE(my_formats); ++i) {
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if (my_formats[i].format == in_format)
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break;
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}
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if (i >= ARRAY_SIZE(my_formats)) {
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pr_err("%s: bad input format\n", __func__);
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- i = 4;
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+ i = ARRAY_SIZE(my_formats) - 1;
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}
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- if (BUS_FMT_IS_BGR(bus_format))
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- i ^= 1;
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- shift = my_formats[i].shift;
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- imask = my_formats[i].mask;
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- rgbsz = my_formats[i].rgbsz;
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+
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+ /*
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+ * Although these RGB orderings refer to the output (DPI bus) format,
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+ * here we permute the *input* components. After this point, "Red"
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+ * will be most significant (highest numbered GPIOs), regardless
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+ * of rgb_order or bus_format. This simplifies later workarounds.
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+ */
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+ order = dpi->rgb_order_override;
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+ if (order == RP1DPI_ORDER_UNCHANGED)
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+ order = BUS_FMT_IS_BGR(bus_format) ? RP1DPI_ORDER_BGR : RP1DPI_ORDER_RGB;
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+ rgb_code[0] = my_formats[i].rgb_code[order & 3];
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+ rgb_code[1] = my_formats[i].rgb_code[(order >> 8) & 3];
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+ rgb_code[2] = my_formats[i].rgb_code[(order >> 16) & 3];
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+ rgbsz = FIELD_PREP(DPI_DMA_RGBSZ_BPP_MASK, my_formats[i].bpp) |
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+ FIELD_PREP(DPI_DMA_RGBSZ_R_MASK, RGB_SCALE(rgb_code[0])) |
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+ FIELD_PREP(DPI_DMA_RGBSZ_G_MASK, RGB_SCALE(rgb_code[1])) |
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+ FIELD_PREP(DPI_DMA_RGBSZ_B_MASK, RGB_SCALE(rgb_code[2]));
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+ shift = FIELD_PREP(DPI_DMA_SHIFT_IR_MASK, RGB_SHIFT(rgb_code[0])) |
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+ FIELD_PREP(DPI_DMA_SHIFT_IG_MASK, RGB_SHIFT(rgb_code[1])) |
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+ FIELD_PREP(DPI_DMA_SHIFT_IB_MASK, RGB_SHIFT(rgb_code[2]));
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+ imask = FIELD_PREP(DPI_DMA_IMASK_R_MASK, RGB_MASK(rgb_code[0])) |
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+ FIELD_PREP(DPI_DMA_IMASK_G_MASK, RGB_MASK(rgb_code[1])) |
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+ FIELD_PREP(DPI_DMA_IMASK_B_MASK, RGB_MASK(rgb_code[2]));
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omask = set_output_format(bus_format, &shift, &imask, &rgbsz);
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+ /*
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+ * Configure all DPI/DMA block registers, except base address.
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+ * DMA will not actually start until a FB base address is specified
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+ * using rp1dpi_hw_update().
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+ */
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rp1dpi_hw_write(dpi, DPI_DMA_IMASK, imask);
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rp1dpi_hw_write(dpi, DPI_DMA_OMASK, omask);
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rp1dpi_hw_write(dpi, DPI_DMA_SHIFT, shift);
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