24ade65ab5
This patch series will provide better support for Mediatek ethernet and add support for Airoha AN8855. Signed-off-by: Shiji Yang <yangshiji66@qq.com>
79 lines
2.7 KiB
Diff
79 lines
2.7 KiB
Diff
From 7562da9454c1a6eff3db3b41c183e03039e855e6 Mon Sep 17 00:00:00 2001
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From: Weijie Gao <weijie.gao@mediatek.com>
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Date: Tue, 17 Dec 2024 16:39:27 +0800
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Subject: [PATCH 04/10] net: mediatek: correct register name of ethsys syscfg1
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The SYSCFG0 should be SYSCFG1 according to the programming guide.
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Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
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---
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drivers/net/mtk_eth.c | 14 +++++++-------
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drivers/net/mtk_eth.h | 12 ++++++------
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2 files changed, 13 insertions(+), 13 deletions(-)
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--- a/drivers/net/mtk_eth.c
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+++ b/drivers/net/mtk_eth.c
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@@ -1450,8 +1450,8 @@ static void mtk_mac_init(struct mtk_eth_
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}
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ge_mode = GE_MODE_RGMII;
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- mtk_ethsys_rmw(priv, ETHSYS_SYSCFG0_REG, SYSCFG0_SGMII_SEL_M,
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- SYSCFG0_SGMII_SEL(priv->gmac_id));
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+ mtk_ethsys_rmw(priv, ETHSYS_SYSCFG1_REG, SYSCFG1_SGMII_SEL_M,
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+ SYSCFG1_SGMII_SEL(priv->gmac_id));
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if (priv->phy_interface == PHY_INTERFACE_MODE_SGMII)
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mtk_sgmii_an_init(priv);
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else
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@@ -1469,9 +1469,9 @@ static void mtk_mac_init(struct mtk_eth_
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}
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/* set the gmac to the right mode */
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- mtk_ethsys_rmw(priv, ETHSYS_SYSCFG0_REG,
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- SYSCFG0_GE_MODE_M << SYSCFG0_GE_MODE_S(priv->gmac_id),
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- ge_mode << SYSCFG0_GE_MODE_S(priv->gmac_id));
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+ mtk_ethsys_rmw(priv, ETHSYS_SYSCFG1_REG,
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+ SYSCFG1_GE_MODE_M << SYSCFG1_GE_MODE_S(priv->gmac_id),
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+ ge_mode << SYSCFG1_GE_MODE_S(priv->gmac_id));
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if (priv->force_mode) {
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mcr = (IPG_96BIT_WITH_SHORT_IPG << IPG_CFG_S) |
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@@ -1527,8 +1527,8 @@ static void mtk_xmac_init(struct mtk_eth
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}
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/* Set GMAC to the correct mode */
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- mtk_ethsys_rmw(priv, ETHSYS_SYSCFG0_REG,
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- SYSCFG0_GE_MODE_M << SYSCFG0_GE_MODE_S(priv->gmac_id),
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+ mtk_ethsys_rmw(priv, ETHSYS_SYSCFG1_REG,
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+ SYSCFG1_GE_MODE_M << SYSCFG1_GE_MODE_S(priv->gmac_id),
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0);
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if (priv->phy_interface == PHY_INTERFACE_MODE_USXGMII &&
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--- a/drivers/net/mtk_eth.h
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+++ b/drivers/net/mtk_eth.h
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@@ -65,11 +65,11 @@ enum mkt_eth_capabilities {
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/* Ethernet subsystem registers */
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-#define ETHSYS_SYSCFG0_REG 0x14
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-#define SYSCFG0_GE_MODE_S(n) (12 + ((n) * 2))
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-#define SYSCFG0_GE_MODE_M 0x3
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-#define SYSCFG0_SGMII_SEL_M (0x3 << 8)
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-#define SYSCFG0_SGMII_SEL(gmac) ((!(gmac)) ? BIT(9) : BIT(8))
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+#define ETHSYS_SYSCFG1_REG 0x14
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+#define SYSCFG1_GE_MODE_S(n) (12 + ((n) * 2))
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+#define SYSCFG1_GE_MODE_M 0x3
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+#define SYSCFG1_SGMII_SEL_M (0x3 << 8)
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+#define SYSCFG1_SGMII_SEL(gmac) ((!(gmac)) ? BIT(9) : BIT(8))
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#define ETHSYS_CLKCFG0_REG 0x2c
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#define ETHSYS_TRGMII_CLK_SEL362_5 BIT(11)
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@@ -84,7 +84,7 @@ enum mkt_eth_capabilities {
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#define QPHY_SEL_MASK 0x3
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#define SGMII_QPHY_SEL 0x2
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-/* SYSCFG0_GE_MODE: GE Modes */
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+/* SYSCFG1_GE_MODE: GE Modes */
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#define GE_MODE_RGMII 0
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#define GE_MODE_MII 1
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#define GE_MODE_MII_PHY 2
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