From d2cdc83fb2c7360856e598810b88211d815fc851 Mon Sep 17 00:00:00 2001 From: Ziyang Huang Date: Sun, 8 Sep 2024 16:40:12 +0800 Subject: [PATCH 2/3] arm64: dts: qcom: ipq5018: add mdio node The IPQ5018 SoC contains two MDIO controllers. MDIO0 is used to control its internal GE Phy, while MDIO1 is wired to external PHYs/switch. Signed-off-by: Ziyang Huang Signed-off-by: George Moussalem --- arch/arm64/boot/dts/qcom/ipq5018.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi @@ -192,6 +192,26 @@ status = "disabled"; }; + mdio0: mdio@88000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "qcom,ipq5018-mdio", "qcom,qca-mdio"; + reg = <0x88000 0x64>; + clocks = <&gcc GCC_MDIO0_AHB_CLK>; + clock-names = "gcc_mdio_ahb_clk"; + status = "disabled"; + }; + + mdio1: mdio@90000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "qcom,ipq5018-mdio"; + reg = <0x90000 0x64>; + clocks = <&gcc GCC_MDIO1_AHB_CLK>; + clock-names = "gcc_mdio_ahb_clk"; + status = "disabled"; + }; + cmn_pll: clock-controller@9b000 { compatible = "qcom,ipq9574-cmn-pll"; reg = <0x0009b000 0x800>,