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mediatek: update patch add PWM support for MT7981

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Update patch with version submitted upstream.

Signed-off-by: Daniel Golle <daniel@makrotopia.org>
This commit is contained in:
Daniel Golle 2023-04-20 18:34:47 +01:00
parent 7cbe34170e
commit c68c71eaa9
1 changed files with 29 additions and 119 deletions
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148
target/linux/mediatek/patches-5.15/811-pwm-mediatek-Add-support-for-MT7981.patch
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@ -1,6 +1,6 @@
From 947b535ebfe161e1725f1030a09de10d1460371c Mon Sep 17 00:00:00 2001 From 73d20ebc21c562fbe79d02fa0fa38e095e716fa9 Mon Sep 17 00:00:00 2001
From: Daniel Golle <daniel@makrotopia.org> From: Daniel Golle <daniel@makrotopia.org>
Date: Mon, 23 Jan 2023 20:47:34 +0000 Date: Wed, 19 Apr 2023 20:25:51 +0100
Subject: [PATCH] pwm: mediatek: Add support for MT7981 Subject: [PATCH] pwm: mediatek: Add support for MT7981
The PWM unit on MT7981 uses different register offsets than previous The PWM unit on MT7981 uses different register offsets than previous
@ -10,27 +10,20 @@ used for a temperature controlled fan.
Signed-off-by: Daniel Golle <daniel@makrotopia.org> Signed-off-by: Daniel Golle <daniel@makrotopia.org>
--- ---
drivers/pwm/pwm-mediatek.c | 54 ++++++++++++++++++++++++++++++++------ drivers/pwm/pwm-mediatek.c | 41 ++++++++++++++++++++++++++++++--------
1 file changed, 46 insertions(+), 8 deletions(-) 1 file changed, 33 insertions(+), 8 deletions(-)
--- a/drivers/pwm/pwm-mediatek.c --- a/drivers/pwm/pwm-mediatek.c
+++ b/drivers/pwm/pwm-mediatek.c +++ b/drivers/pwm/pwm-mediatek.c
@@ -34,10 +34,14 @@ @@ -38,6 +38,7 @@ struct pwm_mediatek_of_data {
#define PWM_CLK_DIV_MAX 7
+#define REG_V1 1
+#define REG_V2 2
+
struct pwm_mediatek_of_data {
unsigned int num_pwms; unsigned int num_pwms;
bool pwm45_fixup; bool pwm45_fixup;
bool has_ck_26m_sel; bool has_ck_26m_sel;
+ u8 reg_ver; + const unsigned int *reg_offset;
}; };
/** /**
@@ -59,10 +63,14 @@ struct pwm_mediatek_chip { @@ -59,10 +60,14 @@ struct pwm_mediatek_chip {
const struct pwm_mediatek_of_data *soc; const struct pwm_mediatek_of_data *soc;
}; };
@ -40,169 +33,86 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
}; };
+static const unsigned int mtk_pwm_reg_offset_v2[] = { +static const unsigned int mtk_pwm_reg_offset_v2[] = {
+ 0x0080, 0x00c0, 0x0100, 0x0140, 0x0180, 0x1c0, 0x200, 0x0240 + 0x0080, 0x00c0, 0x0100, 0x0140, 0x0180, 0x01c0, 0x0200, 0x0240
+}; +};
+ +
static inline struct pwm_mediatek_chip * static inline struct pwm_mediatek_chip *
to_pwm_mediatek_chip(struct pwm_chip *chip) to_pwm_mediatek_chip(struct pwm_chip *chip)
{ {
@@ -111,7 +119,19 @@ static inline void pwm_mediatek_writel(s @@ -111,7 +116,7 @@ static inline void pwm_mediatek_writel(s
unsigned int num, unsigned int offset, unsigned int num, unsigned int offset,
u32 value) u32 value)
{ {
- writel(value, chip->regs + pwm_mediatek_reg_offset[num] + offset); - writel(value, chip->regs + pwm_mediatek_reg_offset[num] + offset);
+ u32 pwm_offset; + writel(value, chip->regs + chip->soc->reg_offset[num] + offset);
+
+ switch (chip->soc->reg_ver) {
+ case REG_V2:
+ pwm_offset = mtk_pwm_reg_offset_v2[num];
+ break;
+
+ case REG_V1:
+ default:
+ pwm_offset = mtk_pwm_reg_offset_v1[num];
+ }
+
+ writel(value, chip->regs + pwm_offset + offset);
} }
static int pwm_mediatek_config(struct pwm_chip *chip, struct pwm_device *pwm, static int pwm_mediatek_config(struct pwm_chip *chip, struct pwm_device *pwm,
@@ -146,7 +166,7 @@ static int pwm_mediatek_config(struct pw @@ -270,48 +275,63 @@ static const struct pwm_mediatek_of_data
if (clkdiv > PWM_CLK_DIV_MAX) {
pwm_mediatek_clk_disable(chip, pwm);
- dev_err(chip->dev, "period %d not supported\n", period_ns);
+ dev_err(chip->dev, "period of %d ns not supported\n", period_ns);
return -EINVAL;
}
@@ -221,24 +241,20 @@ static int pwm_mediatek_probe(struct pla
if (IS_ERR(pc->regs))
return PTR_ERR(pc->regs);
- pc->clk_pwms = devm_kcalloc(&pdev->dev, pc->soc->num_pwms,
+ pc->clk_pwms = devm_kmalloc_array(&pdev->dev, pc->soc->num_pwms,
sizeof(*pc->clk_pwms), GFP_KERNEL);
if (!pc->clk_pwms)
return -ENOMEM;
pc->clk_top = devm_clk_get(&pdev->dev, "top");
- if (IS_ERR(pc->clk_top)) {
- dev_err(&pdev->dev, "clock: top fail: %ld\n",
- PTR_ERR(pc->clk_top));
- return PTR_ERR(pc->clk_top);
- }
+ if (IS_ERR(pc->clk_top))
+ return dev_err_probe(&pdev->dev, PTR_ERR(pc->clk_top),
+ "Failed to get top clock\n");
pc->clk_main = devm_clk_get(&pdev->dev, "main");
- if (IS_ERR(pc->clk_main)) {
- dev_err(&pdev->dev, "clock: main fail: %ld\n",
- PTR_ERR(pc->clk_main));
- return PTR_ERR(pc->clk_main);
- }
+ if (IS_ERR(pc->clk_main))
+ return dev_err_probe(&pdev->dev, PTR_ERR(pc->clk_main),
+ "Failed to get main clock\n");
for (i = 0; i < pc->soc->num_pwms; i++) {
char name[8];
@@ -246,11 +262,9 @@ static int pwm_mediatek_probe(struct pla
snprintf(name, sizeof(name), "pwm%d", i + 1);
pc->clk_pwms[i] = devm_clk_get(&pdev->dev, name);
- if (IS_ERR(pc->clk_pwms[i])) {
- dev_err(&pdev->dev, "clock: %s fail: %ld\n",
- name, PTR_ERR(pc->clk_pwms[i]));
- return PTR_ERR(pc->clk_pwms[i]);
- }
+ if (IS_ERR(pc->clk_pwms[i]))
+ return dev_err_probe(&pdev->dev, PTR_ERR(pc->clk_pwms[i]),
+ "Failed to get %s clock\n", name);
}
pc->chip.dev = &pdev->dev;
@@ -258,10 +272,8 @@ static int pwm_mediatek_probe(struct pla
pc->chip.npwm = pc->soc->num_pwms;
ret = devm_pwmchip_add(&pdev->dev, &pc->chip);
- if (ret < 0) {
- dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);
- return ret;
- }
+ if (ret < 0)
+ return dev_err_probe(&pdev->dev, ret, "pwmchip_add() failed\n");
return 0;
}
@@ -270,48 +282,63 @@ static const struct pwm_mediatek_of_data
.num_pwms = 8, .num_pwms = 8,
.pwm45_fixup = false, .pwm45_fixup = false,
.has_ck_26m_sel = false, .has_ck_26m_sel = false,
+ .reg_ver = REG_V1, + .reg_offset = mtk_pwm_reg_offset_v1,
}; };
static const struct pwm_mediatek_of_data mt7622_pwm_data = { static const struct pwm_mediatek_of_data mt7622_pwm_data = {
.num_pwms = 6, .num_pwms = 6,
.pwm45_fixup = false, .pwm45_fixup = false,
.has_ck_26m_sel = true, .has_ck_26m_sel = true,
+ .reg_ver = REG_V1, + .reg_offset = mtk_pwm_reg_offset_v1,
}; };
static const struct pwm_mediatek_of_data mt7623_pwm_data = { static const struct pwm_mediatek_of_data mt7623_pwm_data = {
.num_pwms = 5, .num_pwms = 5,
.pwm45_fixup = true, .pwm45_fixup = true,
.has_ck_26m_sel = false, .has_ck_26m_sel = false,
+ .reg_ver = REG_V1, + .reg_offset = mtk_pwm_reg_offset_v1,
}; };
static const struct pwm_mediatek_of_data mt7628_pwm_data = { static const struct pwm_mediatek_of_data mt7628_pwm_data = {
.num_pwms = 4, .num_pwms = 4,
.pwm45_fixup = true, .pwm45_fixup = true,
.has_ck_26m_sel = false, .has_ck_26m_sel = false,
+ .reg_ver = REG_V1, + .reg_offset = mtk_pwm_reg_offset_v1,
}; };
static const struct pwm_mediatek_of_data mt7629_pwm_data = { static const struct pwm_mediatek_of_data mt7629_pwm_data = {
.num_pwms = 1, .num_pwms = 1,
.pwm45_fixup = false, .pwm45_fixup = false,
.has_ck_26m_sel = false, .has_ck_26m_sel = false,
+ .reg_ver = REG_V1, + .reg_offset = mtk_pwm_reg_offset_v1,
}; };
-static const struct pwm_mediatek_of_data mt8183_pwm_data = { static const struct pwm_mediatek_of_data mt8183_pwm_data = {
- .num_pwms = 4, .num_pwms = 4,
+static const struct pwm_mediatek_of_data mt7981_pwm_data = {
+ .num_pwms = 3,
.pwm45_fixup = false, .pwm45_fixup = false,
.has_ck_26m_sel = true, .has_ck_26m_sel = true,
+ .reg_ver = REG_V2, + .reg_offset = mtk_pwm_reg_offset_v1,
+};
+
+static const struct pwm_mediatek_of_data mt7981_pwm_data = {
+ .num_pwms = 3,
+ .pwm45_fixup = false,
+ .has_ck_26m_sel = true,
+ .reg_offset = mtk_pwm_reg_offset_v2,
}; };
static const struct pwm_mediatek_of_data mt7986_pwm_data = { static const struct pwm_mediatek_of_data mt7986_pwm_data = {
.num_pwms = 2, .num_pwms = 2,
.pwm45_fixup = false, .pwm45_fixup = false,
.has_ck_26m_sel = true, .has_ck_26m_sel = true,
+ .reg_ver = REG_V1, + .reg_offset = mtk_pwm_reg_offset_v1,
+};
+
+static const struct pwm_mediatek_of_data mt8183_pwm_data = {
+ .num_pwms = 4,
+ .pwm45_fixup = false,
+ .has_ck_26m_sel = true,
+ .reg_ver = REG_V1,
}; };
static const struct pwm_mediatek_of_data mt8516_pwm_data = { static const struct pwm_mediatek_of_data mt8516_pwm_data = {
.num_pwms = 5, .num_pwms = 5,
.pwm45_fixup = false, .pwm45_fixup = false,
.has_ck_26m_sel = true, .has_ck_26m_sel = true,
+ .reg_ver = REG_V1, + .reg_offset = mtk_pwm_reg_offset_v1,
}; };
static const struct of_device_id pwm_mediatek_of_match[] = { static const struct of_device_id pwm_mediatek_of_match[] = {
@@ -320,6 +347,7 @@ static const struct of_device_id pwm_med @@ -320,6 +340,7 @@ static const struct of_device_id pwm_med
{ .compatible = "mediatek,mt7623-pwm", .data = &mt7623_pwm_data }, { .compatible = "mediatek,mt7623-pwm", .data = &mt7623_pwm_data },
{ .compatible = "mediatek,mt7628-pwm", .data = &mt7628_pwm_data }, { .compatible = "mediatek,mt7628-pwm", .data = &mt7628_pwm_data },
{ .compatible = "mediatek,mt7629-pwm", .data = &mt7629_pwm_data }, { .compatible = "mediatek,mt7629-pwm", .data = &mt7629_pwm_data },