mediatek: replace patch with version sent upstream
Replace recently added patch 701-net-ethernet-mtk_eth_soc-add-support-for-clause-45-mdio.patch with version sent upstream 701-net-ethernet-mtk_eth_soc-implement-Clause-45-MDIO-access.patch Signed-off-by: Daniel Golle <daniel@makrotopia.org>
This commit is contained in:
Daniel Golle
parent
5deb3996e2
commit
c555c34dd1
@ -1,94 +0,0 @@
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--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
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+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
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@@ -103,10 +103,30 @@ static u32 _mtk_mdio_write(struct mtk_et
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write_data &= 0xffff;
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- mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_WRITE |
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- (phy_register << PHY_IAC_REG_SHIFT) |
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- (phy_addr << PHY_IAC_ADDR_SHIFT) | write_data,
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- MTK_PHY_IAC);
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+ if (phy_register & MII_ADDR_C45) {
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+ u8 dev_num = (phy_register >> 16) & 0x1f;
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+ u16 reg = (u16)(phy_register & 0xffff);
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+
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+ mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START_C45 | PHY_IAC_SET_ADDR |
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+ (phy_addr << PHY_IAC_ADDR_SHIFT) |
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+ (dev_num << PHY_IAC_REG_SHIFT) |
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+ reg,
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+ MTK_PHY_IAC);
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+
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+ if (mtk_mdio_busy_wait(eth))
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+ return 0xffff;
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+
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+ mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START_C45 | PHY_IAC_WRITE |
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+ (phy_addr << PHY_IAC_ADDR_SHIFT) |
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+ (dev_num << PHY_IAC_REG_SHIFT) |
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+ write_data,
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+ MTK_PHY_IAC);
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+ } else {
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+ mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_WRITE |
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+ (phy_register << PHY_IAC_REG_SHIFT) |
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+ (phy_addr << PHY_IAC_ADDR_SHIFT) | write_data,
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+ MTK_PHY_IAC);
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+ }
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if (mtk_mdio_busy_wait(eth))
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return -1;
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@@ -121,10 +141,29 @@ static u32 _mtk_mdio_read(struct mtk_eth
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if (mtk_mdio_busy_wait(eth))
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return 0xffff;
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- mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_READ |
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- (phy_reg << PHY_IAC_REG_SHIFT) |
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- (phy_addr << PHY_IAC_ADDR_SHIFT),
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- MTK_PHY_IAC);
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+ if (phy_reg & MII_ADDR_C45) {
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+ u8 dev_num = (phy_reg >> 16) & 0x1f;
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+ u16 reg = (u16)(phy_reg & 0xffff);
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+
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+ mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START_C45 | PHY_IAC_SET_ADDR |
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+ (phy_addr << PHY_IAC_ADDR_SHIFT) |
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+ (dev_num << PHY_IAC_REG_SHIFT) |
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+ reg,
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+ MTK_PHY_IAC);
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+
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+ if (mtk_mdio_busy_wait(eth))
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+ return 0xffff;
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+
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+ mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START_C45 | PHY_IAC_READ_C45 |
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+ (phy_addr << PHY_IAC_ADDR_SHIFT) |
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+ (dev_num << PHY_IAC_REG_SHIFT),
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+ MTK_PHY_IAC);
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+ } else {
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+ mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_READ |
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+ (phy_reg << PHY_IAC_REG_SHIFT) |
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+ (phy_addr << PHY_IAC_ADDR_SHIFT),
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+ MTK_PHY_IAC);
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+ }
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if (mtk_mdio_busy_wait(eth))
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return 0xffff;
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@@ -584,6 +623,7 @@ static int mtk_mdio_init(struct mtk_eth
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eth->mii_bus->name = "mdio";
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eth->mii_bus->read = mtk_mdio_read;
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eth->mii_bus->write = mtk_mdio_write;
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+ eth->mii_bus->probe_capabilities = MDIOBUS_C22_C45;
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eth->mii_bus->priv = eth;
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eth->mii_bus->parent = eth->dev;
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--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
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+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
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@@ -340,9 +340,12 @@
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/* PHY Indirect Access Control registers */
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#define MTK_PHY_IAC 0x10004
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#define PHY_IAC_ACCESS BIT(31)
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+#define PHY_IAC_SET_ADDR 0
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#define PHY_IAC_READ BIT(19)
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+#define PHY_IAC_READ_C45 (BIT(18) | BIT(19))
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#define PHY_IAC_WRITE BIT(18)
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#define PHY_IAC_START BIT(16)
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+#define PHY_IAC_START_C45 0
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#define PHY_IAC_ADDR_SHIFT 20
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#define PHY_IAC_REG_SHIFT 25
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#define PHY_IAC_TIMEOUT HZ
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@ -0,0 +1,166 @@
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From patchwork Mon Dec 27 16:09:22 2021
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Content-Type: text/plain; charset="utf-8"
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MIME-Version: 1.0
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Content-Transfer-Encoding: 7bit
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X-Patchwork-Submitter: Daniel Golle <daniel@makrotopia.org>
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X-Patchwork-Id: 12699860
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X-Patchwork-Delegate: kuba@kernel.org
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Date: Mon, 27 Dec 2021 16:09:22 +0000
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From: Daniel Golle <daniel@makrotopia.org>
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To: linux-mediatek@lists.infradead.org, netdev@vger.kernel.org,
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linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org
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Cc: Felix Fietkau <nbd@nbd.name>, John Crispin <john@phrozen.org>,
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Sean Wang <sean.wang@mediatek.com>,
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Mark Lee <Mark-MC.Lee@mediatek.com>,
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"David S. Miller" <davem@davemloft.net>,
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Jakub Kicinski <kuba@kernel.org>,
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Matthias Brugger <matthias.bgg@gmail.com>,
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Russell King <linux@armlinux.org.uk>,
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Andrew Lunn <andrew@lunn.ch>
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Subject: [PATCH v3] net: ethernet: mtk_eth_soc: implement Clause 45 MDIO
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access
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Message-ID: <YcnlMtninjjjPhjI@makrotopia.org>
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References: <YcjsFnbg87o45ltd@lunn.ch>
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<YcjjzNJ159Bo1xk7@lunn.ch>
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<YcjlMCacTTJ4RsSA@shell.armlinux.org.uk>
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<YcjepQ2fmkPZ2+pE@makrotopia.org>
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MIME-Version: 1.0
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Content-Disposition: inline
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In-Reply-To: <YcjsFnbg87o45ltd@lunn.ch>
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<YcjjzNJ159Bo1xk7@lunn.ch>
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<YcjlMCacTTJ4RsSA@shell.armlinux.org.uk>
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<YcjepQ2fmkPZ2+pE@makrotopia.org>
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Precedence: bulk
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List-ID: <netdev.vger.kernel.org>
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X-Mailing-List: netdev@vger.kernel.org
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X-Patchwork-Delegate: kuba@kernel.org
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Implement read and write access to IEEE 802.3 Clause 45 Ethernet
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phy registers.
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Tested on the Ubiquiti UniFi 6 LR access point featuring
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MediaTek MT7622BV WiSoC with Aquantia AQR112C.
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Signed-off-by: Daniel Golle <daniel@makrotopia.org>
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---
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v3: return -1 instead of 0xffff on error in _mtk_mdio_write
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v2: use MII_DEVADDR_C45_SHIFT and MII_REGADDR_C45_MASK to extract
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device id and register address. Unify read and write functions to
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have identical types and parameter names where possible as we are
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anyway already replacing both function bodies.
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drivers/net/ethernet/mediatek/mtk_eth_soc.c | 62 +++++++++++++++++----
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drivers/net/ethernet/mediatek/mtk_eth_soc.h | 3 +
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2 files changed, 54 insertions(+), 11 deletions(-)
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--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
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+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
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@@ -95,18 +95,38 @@ static int mtk_mdio_busy_wait(struct mtk
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return -1;
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}
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-static u32 _mtk_mdio_write(struct mtk_eth *eth, u32 phy_addr,
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- u32 phy_register, u32 write_data)
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+static u32 _mtk_mdio_write(struct mtk_eth *eth, u32 phy_addr, u32 phy_reg,
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+ u32 write_data)
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{
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if (mtk_mdio_busy_wait(eth))
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return -1;
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write_data &= 0xffff;
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- mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_WRITE |
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- (phy_register << PHY_IAC_REG_SHIFT) |
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- (phy_addr << PHY_IAC_ADDR_SHIFT) | write_data,
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- MTK_PHY_IAC);
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+ if (phy_reg & MII_ADDR_C45) {
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+ u8 dev_num = (phy_reg >> MII_DEVADDR_C45_SHIFT) & GENMASK(4, 0);
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+ u16 reg = (u16)(phy_reg & MII_REGADDR_C45_MASK);
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+
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+ mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START_C45 | PHY_IAC_SET_ADDR |
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+ (phy_addr << PHY_IAC_ADDR_SHIFT) |
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+ (dev_num << PHY_IAC_REG_SHIFT) |
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+ reg,
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+ MTK_PHY_IAC);
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+
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+ if (mtk_mdio_busy_wait(eth))
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+ return -1;
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+
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+ mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START_C45 | PHY_IAC_WRITE |
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+ (phy_addr << PHY_IAC_ADDR_SHIFT) |
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+ (dev_num << PHY_IAC_REG_SHIFT) |
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+ write_data,
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+ MTK_PHY_IAC);
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+ } else {
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+ mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_WRITE |
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+ (phy_reg << PHY_IAC_REG_SHIFT) |
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+ (phy_addr << PHY_IAC_ADDR_SHIFT) | write_data,
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+ MTK_PHY_IAC);
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+ }
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if (mtk_mdio_busy_wait(eth))
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return -1;
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@@ -114,17 +134,36 @@ static u32 _mtk_mdio_write(struct mtk_et
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return 0;
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}
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-static u32 _mtk_mdio_read(struct mtk_eth *eth, int phy_addr, int phy_reg)
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+static u32 _mtk_mdio_read(struct mtk_eth *eth, u32 phy_addr, u32 phy_reg)
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{
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u32 d;
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if (mtk_mdio_busy_wait(eth))
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return 0xffff;
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- mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_READ |
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- (phy_reg << PHY_IAC_REG_SHIFT) |
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- (phy_addr << PHY_IAC_ADDR_SHIFT),
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- MTK_PHY_IAC);
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+ if (phy_reg & MII_ADDR_C45) {
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+ u8 dev_num = (phy_reg >> MII_DEVADDR_C45_SHIFT) & GENMASK(4, 0);
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+ u16 reg = (u16)(phy_reg & MII_REGADDR_C45_MASK);
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+
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+ mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START_C45 | PHY_IAC_SET_ADDR |
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+ (phy_addr << PHY_IAC_ADDR_SHIFT) |
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+ (dev_num << PHY_IAC_REG_SHIFT) |
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+ reg,
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+ MTK_PHY_IAC);
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+
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+ if (mtk_mdio_busy_wait(eth))
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+ return 0xffff;
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+
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+ mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START_C45 | PHY_IAC_READ_C45 |
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+ (phy_addr << PHY_IAC_ADDR_SHIFT) |
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+ (dev_num << PHY_IAC_REG_SHIFT),
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+ MTK_PHY_IAC);
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+ } else {
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+ mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_READ |
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+ (phy_reg << PHY_IAC_REG_SHIFT) |
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+ (phy_addr << PHY_IAC_ADDR_SHIFT),
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+ MTK_PHY_IAC);
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+ }
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if (mtk_mdio_busy_wait(eth))
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return 0xffff;
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@@ -584,6 +623,7 @@ static int mtk_mdio_init(struct mtk_eth
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eth->mii_bus->name = "mdio";
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eth->mii_bus->read = mtk_mdio_read;
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eth->mii_bus->write = mtk_mdio_write;
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+ eth->mii_bus->probe_capabilities = MDIOBUS_C22_C45;
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eth->mii_bus->priv = eth;
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eth->mii_bus->parent = eth->dev;
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--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
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+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
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@@ -340,9 +340,12 @@
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/* PHY Indirect Access Control registers */
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#define MTK_PHY_IAC 0x10004
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#define PHY_IAC_ACCESS BIT(31)
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+#define PHY_IAC_SET_ADDR 0
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#define PHY_IAC_READ BIT(19)
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+#define PHY_IAC_READ_C45 (BIT(18) | BIT(19))
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#define PHY_IAC_WRITE BIT(18)
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#define PHY_IAC_START BIT(16)
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+#define PHY_IAC_START_C45 0
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#define PHY_IAC_ADDR_SHIFT 20
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#define PHY_IAC_REG_SHIFT 25
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#define PHY_IAC_TIMEOUT HZ
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