diff --git a/target/linux/qualcommax/patches-6.6/0401-spi-dt-bindings-Introduce-qcom-spi-qpic-snand.patch b/target/linux/qualcommax/patches-6.6/0401-spi-dt-bindings-Introduce-qcom-spi-qpic-snand.patch deleted file mode 100644 index 433db36871..0000000000 --- a/target/linux/qualcommax/patches-6.6/0401-spi-dt-bindings-Introduce-qcom-spi-qpic-snand.patch +++ /dev/null @@ -1,97 +0,0 @@ -From: Md Sadre Alam -Date: Sun, 22 Sep 2024 17:03:44 +0530 -Subject: [PATCH] spi: dt-bindings: Introduce qcom,spi-qpic-snand - -Document the QPIC-SPI-NAND flash controller present in the IPQ SoCs. -It can work both in serial and parallel mode and supports typical -SPI-NAND page cache operations. - -Reviewed-by: Krzysztof Kozlowski -Signed-off-by: Md Sadre Alam ---- ---- /dev/null -+++ b/Documentation/devicetree/bindings/spi/qcom,spi-qpic-snand.yaml -@@ -0,0 +1,83 @@ -+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/spi/qcom,spi-qpic-snand.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: Qualcomm QPIC NAND controller -+ -+maintainers: -+ - Md sadre Alam -+ -+description: -+ The QCOM QPIC-SPI-NAND flash controller is an extended version of -+ the QCOM QPIC NAND flash controller. It can work both in serial -+ and parallel mode. It supports typical SPI-NAND page cache -+ operations in single, dual or quad IO mode with pipelined ECC -+ encoding/decoding using the QPIC ECC HW engine. -+ -+allOf: -+ - $ref: /schemas/spi/spi-controller.yaml# -+ -+properties: -+ compatible: -+ enum: -+ - qcom,spi-qpic-snand -+ -+ reg: -+ maxItems: 1 -+ -+ clocks: -+ maxItems: 3 -+ -+ clock-names: -+ items: -+ - const: core -+ - const: aon -+ - const: iom -+ -+ dmas: -+ items: -+ - description: tx DMA channel -+ - description: rx DMA channel -+ - description: cmd DMA channel -+ -+ dma-names: -+ items: -+ - const: tx -+ - const: rx -+ - const: cmd -+ -+required: -+ - compatible -+ - reg -+ - clocks -+ - clock-names -+ -+unevaluatedProperties: false -+ -+examples: -+ - | -+ #include -+ spi@79b0000 { -+ compatible = "qcom,spi-qpic-snand"; -+ reg = <0x1ac00000 0x800>; -+ -+ clocks = <&gcc GCC_QPIC_CLK>, -+ <&gcc GCC_QPIC_AHB_CLK>, -+ <&gcc GCC_QPIC_IO_MACRO_CLK>; -+ clock-names = "core", "aon", "iom"; -+ -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ flash@0 { -+ compatible = "spi-nand"; -+ reg = <0>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ nand-ecc-engine = <&qpic_nand>; -+ nand-ecc-strength = <4>; -+ nand-ecc-step-size = <512>; -+ }; -+ }; diff --git a/target/linux/qualcommax/patches-6.6/0406-spi-spi-qpic-add-driver-for-QCOM-SPI-NAND-flash-Interface.patch b/target/linux/qualcommax/patches-6.6/0409-v14-6-8-spi-spi-qpic-add-driver-for-QCOM-SPI-NAND-flash-Interface.patch similarity index 77% rename from target/linux/qualcommax/patches-6.6/0406-spi-spi-qpic-add-driver-for-QCOM-SPI-NAND-flash-Interface.patch rename to target/linux/qualcommax/patches-6.6/0409-v14-6-8-spi-spi-qpic-add-driver-for-QCOM-SPI-NAND-flash-Interface.patch index 8ad17ff60c..8635746410 100644 --- a/target/linux/qualcommax/patches-6.6/0406-spi-spi-qpic-add-driver-for-QCOM-SPI-NAND-flash-Interface.patch +++ b/target/linux/qualcommax/patches-6.6/0409-v14-6-8-spi-spi-qpic-add-driver-for-QCOM-SPI-NAND-flash-Interface.patch @@ -1,6 +1,188 @@ +From patchwork Wed Nov 20 09:15:04 2024 +Content-Type: text/plain; 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The original + message has been attached to this so you can view it or label + similar future email. If you have any questions, see + the administrator of that system for details. + Content preview: This driver implements support for the SPI-NAND mode of + QCOM + NAND Flash Interface as a SPI-MEM controller with pipelined ECC + capability. + Co-developed-by: Sricharan Ramabadhran + Signed-off-by: + Sricharan Ramabadhran Co-developed-by: + Varadarajan + Narayanan Sig [...] + Content analysis details: (-2.8 points, 5.0 required) + pts rule name description + ---- ---------------------- + -------------------------------------------------- + 0.0 RCVD_IN_VALIDITY_RPBL_BLOCKED RBL: ADMINISTRATOR NOTICE: The query to + Validity was blocked. See + https://knowledge.validity.com/hc/en-us/articles/20961730681243 + for more information. + [205.220.180.131 listed in + bl.score.senderscore.com] + 0.0 RCVD_IN_VALIDITY_SAFE_BLOCKED RBL: ADMINISTRATOR NOTICE: The query to + Validity was blocked. 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implements support for the SPI-NAND mode of QCOM NAND Flash Interface as a SPI-MEM controller with pipelined ECC capability. @@ -11,6 +193,192 @@ Co-developed-by: Varadarajan Narayanan Signed-off-by: Varadarajan Narayanan Signed-off-by: Md Sadre Alam --- + +Change in [v14] + +* No Change + +Change in [v13] + +* Changed return type of qcom_spi_cmd_mapping() from u32 to + int to fix the kernel test bot warning +* Changed type of variable cmd in qcom_spi_write_page() from u32 + to int +* Removed unused variable s_op from qcom_spi_write_page() +* Updated return value variable type from u32 to int in + qcom_spi_send_cmdaddr() + +Change in [v12] + +* Added obj-$(CONFIG_SPI_QPIC_SNAND) += qpic_common.o in Makefile + to build qpic_common.c based on CONFIG_SPI_QPIC_SNAND + +Change in [v11] + +* Fixed build error reported by kernel test bot +* Changed "depends on MTD" to "select MTD" in + drivers/spi/Kconfig file + +Change in [v10] + +* Fixed compilation warnings reported by kernel test robot. +* Added depends on CONFIG_MTD +* removed extra bracket from statement if (i == (num_cw - 1)) in + qcom_spi_program_raw() api. + +Change in [v9] + +* Changed data type of addr1, addr2, cmd, to __le32 in qpic_spi_nand + structure +* In qcom_spi_set_read_loc_first() api added cpu_to_le32() macro to fix + compilation warning +* In qcom_spi_set_read_loc_last() api added cpu_to_le32() macro to fix + compilation warning +* In qcom_spi_init() api added cpu_to_le32() macro to fix compilation + warning +* In qcom_spi_ecc_init_ctx_pipelined() api removed unused variables + reqs, user, step_size, strength and added cpu_to_le32() macro as well + to fix compilation warning +* In qcom_spi_read_last_cw() api added cpu_to_le32() macro to fix compilation + warning +* In qcom_spi_check_error() api added cpu_to_le32() macro to fix compilation + warning +* In qcom_spi_read_page_ecc() api added cpu_to_le32() macro to fix compilation + warning +* In qcom_spi_read_page_oob() api added cpu_to_le32() macro to fix compilation + warning +* In qcom_spi_program_raw() api added cpu_to_le32() macro to fix compilation + warning +* In qcom_spi_program_ecc() api added cpu_to_le32() macro to fix compilation + warning +* In qcom_spi_program_oob() api added cpu_to_le32() macro to fix compilation + warning +* In qcom_spi_send_cmdaddr() api added cpu_to_le32() macro to fix compilation + warning +* In qcom_spi_io_op() api added cpu_to_le32() macro to fix compilation + warning + +Change in [v8] + +* Included "bitfield.h" file to /spi-qpic-snand.c + to fix compilation warning reported by kernel test robot +* Removed unused variable "steps" in + qcom_spi_ecc_init_ctx_pipelined() to fix compilation warning + +Change in [v7] + +* Added read_oob() and write_oob() api + +* Handled offset value for oob layout + +* Made CONFIG_SPI_QPIC_SNAND as bool + +* Added macro ecceng_to_qspi() + +* Added FIELD_PREP() Macro in spi init + +* Added else condition in + qcom_spi_ecc_finish_io_req_pipelined() + for corrected ecc + +* Handled multiple error condition for api + qcom_spi_cmd_mapping() + +* Fix typo for printing debug message + +Change in [v6] + +* Added separate qpic_spi_nand{...} struct + +* moved qpic_ecc and qcom_ecc_stats struct to + spi-qpic-snand.c file, since its spi nand + specific + +* Added FIELD_PREP() and GENMASK() macro + +* Removed rawnand.h and partition.h from + spi-qpic-snand.c + +* Removed oob_buff assignment form + qcom_spi_write_page_cache + +* Added qcom_nand_unalloc() in remove() path + +* Fixes all all comments + +Change in [v5] + +* Added raw_read() and raw_write() api + +* Updated commit message + +* Removed register indirection + +* Added qcom_spi_ prefix to all the api + +* Removed snand_set_reg() api. + +* Fixed nandbiterr issue + +* Removed hardcoded num_cw and made it variable + +* Removed hardcoded value for mtd pagesize + +* Added -ENOSUPPORT in cmd mapping for unsupported + commands + +* Replace if..else with switch..case statement + +Change in [v4] + +* No change + +Change in [v3] + +* Set SPI_QPIC_SNAND to n and added COMPILE_TEST in Kconfig + +* Made driver name sorted in Make file + +* Made comment like c++ + +* Changed macro to functions, snandc_set_read_loc_last() + and snandc_set_read_loc_first() + +* Added error handling in snandc_set_reg() + +* Changed into normal conditional statement for + return snandc->ecc_stats.failed ? -EBADMSG : + snandc->ecc_stats.bitflips; + +* Remove cast of wbuf in qpic_snand_program_execute() + function + +* Made num_cw variable instead hardcoded value + +* changed if..else condition of function qpic_snand_io_op() + to switch..case statement + +* Added __devm_spi_alloc_controller() api instead of + devm_spi_alloc_master() + +* Disabling clock in remove path + +Change in [v2] + +* Added initial support for SPI-NAND driver + +Change in [v1] + +* Added RFC patch for design review + + drivers/mtd/nand/Makefile | 4 + + drivers/spi/Kconfig | 9 + + drivers/spi/Makefile | 1 + + drivers/spi/spi-qpic-snand.c | 1633 ++++++++++++++++++++++++++ + include/linux/mtd/nand-qpic-common.h | 7 + + 5 files changed, 1654 insertions(+) + create mode 100644 drivers/spi/spi-qpic-snand.c + --- a/drivers/mtd/nand/Makefile +++ b/drivers/mtd/nand/Makefile @@ -4,7 +4,11 @@ nandcore-objs := core.o bbt.o @@ -27,13 +395,14 @@ Signed-off-by: Md Sadre Alam obj-y += spi/ --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig -@@ -870,6 +870,14 @@ config SPI_QCOM_QSPI +@@ -870,6 +870,15 @@ config SPI_QCOM_QSPI help QSPI(Quad SPI) driver for Qualcomm QSPI controller. +config SPI_QPIC_SNAND + bool "QPIC SNAND controller" + depends on ARCH_QCOM || COMPILE_TEST ++ select MTD + help + QPIC_SNAND (QPIC SPI NAND) driver for Qualcomm QPIC controller. + QPIC controller supports both parallel nand and serial nand. @@ -54,7 +423,7 @@ Signed-off-by: Md Sadre Alam obj-$(CONFIG_SPI_ROCKCHIP_SFC) += spi-rockchip-sfc.o --- /dev/null +++ b/drivers/spi/spi-qpic-snand.c -@@ -0,0 +1,1634 @@ +@@ -0,0 +1,1633 @@ +/* + * SPDX-License-Identifier: GPL-2.0 + * @@ -1072,7 +1441,7 @@ Signed-off-by: Md Sadre Alam + data_size1 = mtd->writesize - ecc_cfg->cw_size * (num_cw - 1); + oob_size1 = ecc_cfg->bbm_size; + -+ if ((i == (num_cw - 1))) { ++ if (i == (num_cw - 1)) { + data_size2 = NANDC_STEP_SIZE - data_size1 - + ((num_cw - 1) << 2); + oob_size2 = (num_cw << 2) + ecc_cfg->ecc_bytes_hw + @@ -1257,9 +1626,9 @@ Signed-off-by: Md Sadre Alam + return 0; +} + -+static u32 qcom_spi_cmd_mapping(struct qcom_nand_controller *snandc, u32 opcode) ++static int qcom_spi_cmd_mapping(struct qcom_nand_controller *snandc, u32 opcode) +{ -+ u32 cmd = 0x0; ++ int cmd = 0x0; + + switch (opcode) { + case SPINAND_RESET: @@ -1310,15 +1679,12 @@ Signed-off-by: Md Sadre Alam +static int qcom_spi_write_page(struct qcom_nand_controller *snandc, + const struct spi_mem_op *op) +{ -+ struct qpic_snand_op s_op = {}; -+ u32 cmd; ++ int cmd; + + cmd = qcom_spi_cmd_mapping(snandc, op->cmd.opcode); + if (cmd < 0) + return cmd; + -+ s_op.cmd_reg = cmd; -+ + if (op->cmd.opcode == SPINAND_PROGRAM_LOAD) + snandc->qspi->data_buf = (u8 *)op->data.buf.out; + @@ -1332,9 +1698,11 @@ Signed-off-by: Md Sadre Alam + u32 cmd; + int ret, opcode; + -+ cmd = qcom_spi_cmd_mapping(snandc, op->cmd.opcode); -+ if (cmd < 0) -+ return cmd; ++ ret = qcom_spi_cmd_mapping(snandc, op->cmd.opcode); ++ if (ret < 0) ++ return ret; ++ ++ cmd = ret; + + s_op.cmd_reg = cmd; + s_op.addr1_reg = op->addr.val; @@ -1668,7 +2036,7 @@ Signed-off-by: Md Sadre Alam + +static const struct of_device_id qcom_snandc_of_match[] = { + { -+ .compatible = "qcom,spi-qpic-snand", ++ .compatible = "qcom,ipq9574-snand", + .data = &ipq9574_snandc_props, + }, + {} @@ -1681,7 +2049,7 @@ Signed-off-by: Md Sadre Alam + .of_match_table = qcom_snandc_of_match, + }, + .probe = qcom_spi_probe, -+ .remove = qcom_spi_remove, ++ .remove_new = qcom_spi_remove, +}; +module_platform_driver(qcom_spi_driver); + diff --git a/target/linux/qualcommax/patches-6.6/0410-spi-spi-qpic-fix-broken-driver-with-SPINAND_SET_FEAT.patch b/target/linux/qualcommax/patches-6.6/0410-spi-spi-qpic-fix-broken-driver-with-SPINAND_SET_FEAT.patch new file mode 100644 index 0000000000..d39d9588d9 --- /dev/null +++ b/target/linux/qualcommax/patches-6.6/0410-spi-spi-qpic-fix-broken-driver-with-SPINAND_SET_FEAT.patch @@ -0,0 +1,125 @@ +From 8716f3c03d9f71ed0bd12a26f6e9d1e85cff0d12 Mon Sep 17 00:00:00 2001 +From: Christian Marangi +Date: Thu, 30 Jan 2025 00:27:22 +0100 +Subject: [PATCH 1/2] spi: spi-qpic: fix broken driver with SPINAND_SET_FEATURE + command + +The driver always return probe error with SPINAND_SET_FEATURE command: + +spi-nand: probe of spi0.0 failed with error -1207959538 + +The error doesn't match any expected negative error but instead seems to +be an u32 converted to an int. Investigating the entire codeflow I +reached the culprit: qcom_spi_cmd_mapping. + +Such function can return -EOPNOTSUPP or the cmd to run. Problem is that +in the specific context of SPINAND_SET_FEATURE, BIT(31) is set that in +the context of an integer, it gets treated as a negative value. + +To correctly handle this, rework the function to return 0 or a "correct" +negative error and pass a pointer to store the cmd. + +Signed-off-by: Christian Marangi +--- + drivers/spi/spi-qpic-snand.c | 40 +++++++++++++++++------------------- + 1 file changed, 19 insertions(+), 21 deletions(-) + +--- a/drivers/spi/spi-qpic-snand.c ++++ b/drivers/spi/spi-qpic-snand.c +@@ -1200,64 +1200,64 @@ static int qcom_spi_program_execute(stru + return 0; + } + +-static int qcom_spi_cmd_mapping(struct qcom_nand_controller *snandc, u32 opcode) ++static int qcom_spi_cmd_mapping(struct qcom_nand_controller *snandc, u32 opcode, ++ u32 *cmd) + { +- int cmd = 0x0; +- + switch (opcode) { + case SPINAND_RESET: +- cmd = (SPI_WP | SPI_HOLD | SPI_TRANSFER_MODE_x1 | OP_RESET_DEVICE); ++ *cmd = (SPI_WP | SPI_HOLD | SPI_TRANSFER_MODE_x1 | OP_RESET_DEVICE); + break; + case SPINAND_READID: +- cmd = (SPI_WP | SPI_HOLD | SPI_TRANSFER_MODE_x1 | OP_FETCH_ID); ++ *cmd = (SPI_WP | SPI_HOLD | SPI_TRANSFER_MODE_x1 | OP_FETCH_ID); + break; + case SPINAND_GET_FEATURE: +- cmd = (SPI_TRANSFER_MODE_x1 | SPI_WP | SPI_HOLD | ACC_FEATURE); ++ *cmd = (SPI_TRANSFER_MODE_x1 | SPI_WP | SPI_HOLD | ACC_FEATURE); + break; + case SPINAND_SET_FEATURE: +- cmd = (SPI_TRANSFER_MODE_x1 | SPI_WP | SPI_HOLD | ACC_FEATURE | ++ *cmd = (SPI_TRANSFER_MODE_x1 | SPI_WP | SPI_HOLD | ACC_FEATURE | + QPIC_SET_FEATURE); + break; + case SPINAND_READ: + if (snandc->qspi->raw_rw) { +- cmd = (PAGE_ACC | LAST_PAGE | SPI_TRANSFER_MODE_x1 | ++ *cmd = (PAGE_ACC | LAST_PAGE | SPI_TRANSFER_MODE_x1 | + SPI_WP | SPI_HOLD | OP_PAGE_READ); + } else { +- cmd = (PAGE_ACC | LAST_PAGE | SPI_TRANSFER_MODE_x1 | ++ *cmd = (PAGE_ACC | LAST_PAGE | SPI_TRANSFER_MODE_x1 | + SPI_WP | SPI_HOLD | OP_PAGE_READ_WITH_ECC); + } + + break; + case SPINAND_ERASE: +- cmd = OP_BLOCK_ERASE | PAGE_ACC | LAST_PAGE | SPI_WP | ++ *cmd = OP_BLOCK_ERASE | PAGE_ACC | LAST_PAGE | SPI_WP | + SPI_HOLD | SPI_TRANSFER_MODE_x1; + break; + case SPINAND_WRITE_EN: +- cmd = SPINAND_WRITE_EN; ++ *cmd = SPINAND_WRITE_EN; + break; + case SPINAND_PROGRAM_EXECUTE: +- cmd = (PAGE_ACC | LAST_PAGE | SPI_TRANSFER_MODE_x1 | ++ *cmd = (PAGE_ACC | LAST_PAGE | SPI_TRANSFER_MODE_x1 | + SPI_WP | SPI_HOLD | OP_PROGRAM_PAGE); + break; + case SPINAND_PROGRAM_LOAD: +- cmd = SPINAND_PROGRAM_LOAD; ++ *cmd = SPINAND_PROGRAM_LOAD; + break; + default: + dev_err(snandc->dev, "Opcode not supported: %u\n", opcode); + return -EOPNOTSUPP; + } + +- return cmd; ++ return 0; + } + + static int qcom_spi_write_page(struct qcom_nand_controller *snandc, + const struct spi_mem_op *op) + { +- int cmd; ++ u32 cmd; ++ int ret; + +- cmd = qcom_spi_cmd_mapping(snandc, op->cmd.opcode); +- if (cmd < 0) +- return cmd; ++ ret = qcom_spi_cmd_mapping(snandc, op->cmd.opcode, &cmd); ++ if (ret < 0) ++ return ret; + + if (op->cmd.opcode == SPINAND_PROGRAM_LOAD) + snandc->qspi->data_buf = (u8 *)op->data.buf.out; +@@ -1272,12 +1272,10 @@ static int qcom_spi_send_cmdaddr(struct + u32 cmd; + int ret, opcode; + +- ret = qcom_spi_cmd_mapping(snandc, op->cmd.opcode); ++ ret = qcom_spi_cmd_mapping(snandc, op->cmd.opcode, &cmd); + if (ret < 0) + return ret; + +- cmd = ret; +- + s_op.cmd_reg = cmd; + s_op.addr1_reg = op->addr.val; + s_op.addr2_reg = 0; diff --git a/target/linux/qualcommax/patches-6.6/0421-arm64-dts-qcom-ipq5018-Add-SPI-nand-node.patch b/target/linux/qualcommax/patches-6.6/0421-arm64-dts-qcom-ipq5018-Add-SPI-nand-node.patch index 2de155637f..2d4c8c80b6 100644 --- a/target/linux/qualcommax/patches-6.6/0421-arm64-dts-qcom-ipq5018-Add-SPI-nand-node.patch +++ b/target/linux/qualcommax/patches-6.6/0421-arm64-dts-qcom-ipq5018-Add-SPI-nand-node.patch @@ -29,7 +29,7 @@ Signed-off-by: George Moussalem + }; + + qpic_nand: qpic-nand@79b0000 { -+ compatible = "qcom,spi-qpic-snand"; ++ compatible = "qcom,ipq5018-snand", "qcom,ipq9574-snand"; + reg = <0x079b0000 0x10000>; + #address-cells = <1>; + #size-cells = <0>;