sunxi: add support for H616 SoC and Orangepi Zero 2
Specifications: SoC: Allwinner H616 @ 1.5 Ghz DRAM: 1Gb LPDDR3 Power: 5V USB-C Video: HDMI (Type 2.0A - micro) Network: 10/100/1000Mbps Ethernet (Realtek RTL8211F), AW859A BT+wifi Storage: microSD / 2Mb SPI flash USB: 1 USB2.0 Host Debug Serial UART Flashing instructions: Standard sunxi SD card installation procedure - copy image to SD card, insert into SD card slot on the device and boot. Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
This commit is contained in:
Zoltan HERPAI
parent
794349a28a
commit
12584395dc
@ -36,9 +36,15 @@ define Trusted-Firmware-A/sunxi-h6
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PLAT:=sun50i_h6
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PLAT:=sun50i_h6
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endef
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endef
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define Trusted-Firmware-A/sunxi-h616
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NAME:=Allwinner H616
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PLAT:=sun50i_h616
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endef
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TFA_TARGETS:= \
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TFA_TARGETS:= \
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sunxi-a64 \
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sunxi-a64 \
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sunxi-h6
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sunxi-h6 \
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sunxi-h616
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define Package/trusted-firmware-a/install
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define Package/trusted-firmware-a/install
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$(INSTALL_DIR) $(STAGING_DIR_IMAGE)
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$(INSTALL_DIR) $(STAGING_DIR_IMAGE)
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@ -328,6 +328,15 @@ define U-Boot/orangepi_pc2
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ATF:=a64
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ATF:=a64
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endef
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endef
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define U-Boot/orangepi_zero2
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BUILD_SUBTARGET:=cortexa53
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NAME:=Xunlong Orange Pi Zero2
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BUILD_DEVICES:=xunlong_orangepi-zero2
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DEPENDS:=+PACKAGE_u-boot-orangepi_zero2:trusted-firmware-a-sunxi-h616
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UENV:=h616
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ATF:=h616
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endef
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define U-Boot/Bananapi_M2_Ultra
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define U-Boot/Bananapi_M2_Ultra
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BUILD_SUBTARGET:=cortexa7
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BUILD_SUBTARGET:=cortexa7
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NAME:=Bananapi M2 Ultra
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NAME:=Bananapi M2 Ultra
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@ -382,6 +391,7 @@ UBOOT_TARGETS := \
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orangepi_plus \
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orangepi_plus \
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orangepi_2 \
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orangepi_2 \
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orangepi_pc2 \
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orangepi_pc2 \
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orangepi_zero2 \
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pangolin \
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pangolin \
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pine64_plus \
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pine64_plus \
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Sinovoip_BPI_M3 \
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Sinovoip_BPI_M3 \
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7
package/boot/uboot-sunxi/uEnv-h616.txt
Normal file
7
package/boot/uboot-sunxi/uEnv-h616.txt
Normal file
@ -0,0 +1,7 @@
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setenv mmc_rootpart 2
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part uuid mmc ${mmc_bootdev}:${mmc_rootpart} uuid
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setenv loadkernel fatload mmc \$mmc_bootdev \$kernel_addr_r uImage
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setenv loaddtb fatload mmc \$mmc_bootdev \$fdt_addr_r dtb
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setenv bootargs console=ttyS0,115200 earlyprintk root=PARTUUID=${uuid} rootwait
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setenv uenvcmd run loadkernel \&\& run loaddtb \&\& booti \$kernel_addr_r - \$fdt_addr_r
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run uenvcmd
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@ -66,6 +66,8 @@ CONFIG_PINCTRL_SUN50I_A64_R=y
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CONFIG_PINCTRL_SUN50I_H5=y
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CONFIG_PINCTRL_SUN50I_H5=y
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CONFIG_PINCTRL_SUN50I_H6=y
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CONFIG_PINCTRL_SUN50I_H6=y
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CONFIG_PINCTRL_SUN50I_H6_R=y
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CONFIG_PINCTRL_SUN50I_H6_R=y
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CONFIG_PINCTRL_SUN50I_H616=y
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CONFIG_PINCTRL_SUN50I_H616_R=y
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# CONFIG_PREEMPT_DYNAMIC is not set
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# CONFIG_PREEMPT_DYNAMIC is not set
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CONFIG_QUEUED_RWLOCKS=y
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CONFIG_QUEUED_RWLOCKS=y
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CONFIG_QUEUED_SPINLOCKS=y
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CONFIG_QUEUED_SPINLOCKS=y
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@ -83,7 +85,7 @@ CONFIG_SUN50I_A100_R_CCU=y
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CONFIG_SUN50I_A64_CCU=y
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CONFIG_SUN50I_A64_CCU=y
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CONFIG_SUN50I_DE2_BUS=y
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CONFIG_SUN50I_DE2_BUS=y
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CONFIG_SUN50I_ERRATUM_UNKNOWN1=y
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CONFIG_SUN50I_ERRATUM_UNKNOWN1=y
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# CONFIG_SUN50I_H616_CCU is not set
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CONFIG_SUN50I_H616_CCU=y
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CONFIG_SUN50I_H6_CCU=y
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CONFIG_SUN50I_H6_CCU=y
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CONFIG_SUN50I_H6_R_CCU=y
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CONFIG_SUN50I_H6_R_CCU=y
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# CONFIG_SUN6I_RTC_CCU is not set
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# CONFIG_SUN6I_RTC_CCU is not set
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@ -24,6 +24,11 @@ define Device/sun50i-h6
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$(Device/sun50i)
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$(Device/sun50i)
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endef
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endef
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define Device/sun50i-h616
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SOC := sun50i-h616
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$(Device/sun50i)
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endef
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define Device/friendlyarm_nanopi-neo-plus2
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define Device/friendlyarm_nanopi-neo-plus2
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DEVICE_VENDOR := FriendlyARM
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DEVICE_VENDOR := FriendlyARM
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DEVICE_MODEL := NanoPi NEO Plus2
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DEVICE_MODEL := NanoPi NEO Plus2
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@ -108,6 +113,13 @@ define Device/xunlong_orangepi-pc2
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endef
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endef
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TARGET_DEVICES += xunlong_orangepi-pc2
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TARGET_DEVICES += xunlong_orangepi-pc2
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define Device/xunlong_orangepi-zero2
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DEVICE_VENDOR := Xunlong
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DEVICE_MODEL := Orange Pi Zero 2
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$(Device/sun50i-h616)
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endef
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TARGET_DEVICES += xunlong_orangepi-zero2
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define Device/xunlong_orangepi-zero-plus
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define Device/xunlong_orangepi-zero-plus
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DEVICE_VENDOR := Xunlong
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DEVICE_VENDOR := Xunlong
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DEVICE_MODEL := Orange Pi Zero Plus
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DEVICE_MODEL := Orange Pi Zero Plus
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@ -0,0 +1,43 @@
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From e4045c8125d88a9eb8b4f8f74b5c7955d5d9adc0 Mon Sep 17 00:00:00 2001
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From: Andre Przywara <andre.przywara@arm.com>
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Date: Thu, 17 Jun 2021 10:54:22 +0100
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Subject: [PATCH 5000/5006] dt-bindings: usb: Add H616 compatible string
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The Allwinner H616 contains four fully OHCI/EHCI compatible USB host
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controllers, so just add their compatible strings to the list of
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generic OHCI/EHCI controllers.
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Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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---
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Documentation/devicetree/bindings/usb/generic-ehci.yaml | 1 +
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Documentation/devicetree/bindings/usb/generic-ohci.yaml | 1 +
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2 files changed, 2 insertions(+)
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diff --git a/Documentation/devicetree/bindings/usb/generic-ehci.yaml b/Documentation/devicetree/bindings/usb/generic-ehci.yaml
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index c5f629c5bc61..994818cb6044 100644
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--- a/Documentation/devicetree/bindings/usb/generic-ehci.yaml
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+++ b/Documentation/devicetree/bindings/usb/generic-ehci.yaml
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@@ -30,6 +30,7 @@ properties:
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- allwinner,sun4i-a10-ehci
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- allwinner,sun50i-a64-ehci
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- allwinner,sun50i-h6-ehci
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+ - allwinner,sun50i-h616-ehci
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- allwinner,sun5i-a13-ehci
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- allwinner,sun6i-a31-ehci
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- allwinner,sun7i-a20-ehci
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diff --git a/Documentation/devicetree/bindings/usb/generic-ohci.yaml b/Documentation/devicetree/bindings/usb/generic-ohci.yaml
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index f838f78d6164..4fcbd0add49d 100644
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--- a/Documentation/devicetree/bindings/usb/generic-ohci.yaml
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+++ b/Documentation/devicetree/bindings/usb/generic-ohci.yaml
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@@ -20,6 +20,7 @@ properties:
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- allwinner,sun4i-a10-ohci
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- allwinner,sun50i-a64-ohci
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- allwinner,sun50i-h6-ohci
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+ - allwinner,sun50i-h616-ohci
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- allwinner,sun5i-a13-ohci
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- allwinner,sun6i-a31-ohci
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- allwinner,sun7i-a20-ohci
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--
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2.20.1
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@ -0,0 +1,82 @@
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From e2078ae0c559b6ac91db19262b56d8cf334354cb Mon Sep 17 00:00:00 2001
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From: Andre Przywara <andre.przywara@arm.com>
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Date: Mon, 12 Sep 2022 00:03:22 +0100
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Subject: [PATCH 5001/5006] dt-bindings: phy: Add special clock for Allwinner
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H616 PHY
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The USB PHY IP in the Allwinner H616 SoC requires a quirk that involves
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some resources from port 2's PHY and HCI IP. In particular the PMU clock
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for port 2 must be surely ungated before accessing the REG_HCI_PHY_CTL
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register of port 2. To allow each USB port to be controlled
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independently of port 2, we need a handle to that particular PMU clock
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in the *PHY* node, as the HCI and PHY part might be handled by separate
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drivers.
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Add that clock to the requirements of the H616 PHY binding, so that a
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PHY driver can apply the quirk in isolation, without requiring help from
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port 2's HCI driver.
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Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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---
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.../phy/allwinner,sun8i-h3-usb-phy.yaml | 26 +++++++++++++++++++
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1 file changed, 26 insertions(+)
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diff --git a/Documentation/devicetree/bindings/phy/allwinner,sun8i-h3-usb-phy.yaml b/Documentation/devicetree/bindings/phy/allwinner,sun8i-h3-usb-phy.yaml
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index 77539b4601c2..2df012d13655 100644
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--- a/Documentation/devicetree/bindings/phy/allwinner,sun8i-h3-usb-phy.yaml
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+++ b/Documentation/devicetree/bindings/phy/allwinner,sun8i-h3-usb-phy.yaml
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@@ -36,18 +36,22 @@ properties:
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- const: pmu3
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clocks:
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+ minItems: 4
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items:
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- description: USB OTG PHY bus clock
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- description: USB Host 0 PHY bus clock
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- description: USB Host 1 PHY bus clock
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- description: USB Host 2 PHY bus clock
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+ - description: PMU clock for host port 2
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clock-names:
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+ minItems: 4
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items:
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- const: usb0_phy
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- const: usb1_phy
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- const: usb2_phy
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- const: usb3_phy
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+ - const: pmu2_clk
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resets:
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items:
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@@ -96,6 +100,28 @@ required:
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- resets
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- reset-names
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+allOf:
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+ - if:
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+ properties:
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+ compatible:
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+ contains:
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+ enum:
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+ - allwinner,sun50i-h616-usb-phy
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+ then:
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+ properties:
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+ clocks:
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+ minItems: 5
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+
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+ clock-names:
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+ minItems: 5
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+ else:
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+ properties:
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+ clocks:
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+ maxItems: 4
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+
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+ clock-names:
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+ maxItems: 4
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+
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additionalProperties: false
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examples:
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--
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2.20.1
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@ -0,0 +1,190 @@
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From 4cfd9d9350a57fc3ced240dbf61ca2f444283c50 Mon Sep 17 00:00:00 2001
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From: Andre Przywara <andre.przywara@arm.com>
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Date: Wed, 16 Jun 2021 18:20:47 +0100
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Subject: [PATCH 5004/5006] arm64: dts: allwinner: h616: Add USB nodes
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Add the nodes for the MUSB and the four USB host controllers to the SoC
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.dtsi, along with the PHY node needed to bind all of them together.
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EHCI/OHCI and MUSB are compatible to previous SoCs, but the PHY requires
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some quirks (handled in the driver).
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Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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---
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.../arm64/boot/dts/allwinner/sun50i-h616.dtsi | 160 ++++++++++++++++++
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1 file changed, 160 insertions(+)
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diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
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index 622a1f7d1641..74aed0d232a9 100644
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--- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
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+++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
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@@ -504,6 +504,166 @@
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};
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};
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+ usbotg: usb@5100000 {
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+ compatible = "allwinner,sun50i-h616-musb",
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+ "allwinner,sun8i-h3-musb";
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+ reg = <0x05100000 0x0400>;
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+ clocks = <&ccu CLK_BUS_OTG>;
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+ resets = <&ccu RST_BUS_OTG>;
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+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
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+ interrupt-names = "mc";
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+ phys = <&usbphy 0>;
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+ phy-names = "usb";
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+ extcon = <&usbphy 0>;
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+ status = "disabled";
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+ };
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+
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+ usbphy: phy@5100400 {
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+ compatible = "allwinner,sun50i-h616-usb-phy";
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+ reg = <0x05100400 0x24>,
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+ <0x05101800 0x14>,
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+ <0x05200800 0x14>,
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+ <0x05310800 0x14>,
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+ <0x05311800 0x14>;
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+ reg-names = "phy_ctrl",
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+ "pmu0",
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+ "pmu1",
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+ "pmu2",
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+ "pmu3";
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+ clocks = <&ccu CLK_USB_PHY0>,
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+ <&ccu CLK_USB_PHY1>,
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+ <&ccu CLK_USB_PHY2>,
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+ <&ccu CLK_USB_PHY3>,
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+ <&ccu CLK_BUS_EHCI2>;
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+ clock-names = "usb0_phy",
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+ "usb1_phy",
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+ "usb2_phy",
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+ "usb3_phy",
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+ "pmu2_clk";
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+ resets = <&ccu RST_USB_PHY0>,
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+ <&ccu RST_USB_PHY1>,
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+ <&ccu RST_USB_PHY2>,
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+ <&ccu RST_USB_PHY3>;
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+ reset-names = "usb0_reset",
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+ "usb1_reset",
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+ "usb2_reset",
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+ "usb3_reset";
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+ status = "disabled";
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+ #phy-cells = <1>;
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+ };
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+
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+ ehci0: usb@5101000 {
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+ compatible = "allwinner,sun50i-h616-ehci",
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+ "generic-ehci";
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+ reg = <0x05101000 0x100>;
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+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&ccu CLK_BUS_OHCI0>,
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+ <&ccu CLK_BUS_EHCI0>,
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+ <&ccu CLK_USB_OHCI0>;
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+ resets = <&ccu RST_BUS_OHCI0>,
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+ <&ccu RST_BUS_EHCI0>;
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+ phys = <&usbphy 0>;
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+ phy-names = "usb";
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+ status = "disabled";
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+ };
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+
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+ ohci0: usb@5101400 {
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+ compatible = "allwinner,sun50i-h616-ohci",
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+ "generic-ohci";
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+ reg = <0x05101400 0x100>;
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+ interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
+ clocks = <&ccu CLK_BUS_OHCI0>,
|
||||||
|
+ <&ccu CLK_USB_OHCI0>;
|
||||||
|
+ resets = <&ccu RST_BUS_OHCI0>;
|
||||||
|
+ phys = <&usbphy 0>;
|
||||||
|
+ phy-names = "usb";
|
||||||
|
+ status = "disabled";
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ ehci1: usb@5200000 {
|
||||||
|
+ compatible = "allwinner,sun50i-h616-ehci",
|
||||||
|
+ "generic-ehci";
|
||||||
|
+ reg = <0x05200000 0x100>;
|
||||||
|
+ interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
+ clocks = <&ccu CLK_BUS_OHCI1>,
|
||||||
|
+ <&ccu CLK_BUS_EHCI1>,
|
||||||
|
+ <&ccu CLK_USB_OHCI1>;
|
||||||
|
+ resets = <&ccu RST_BUS_OHCI1>,
|
||||||
|
+ <&ccu RST_BUS_EHCI1>;
|
||||||
|
+ phys = <&usbphy 1>;
|
||||||
|
+ phy-names = "usb";
|
||||||
|
+ status = "disabled";
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ ohci1: usb@5200400 {
|
||||||
|
+ compatible = "allwinner,sun50i-h616-ohci",
|
||||||
|
+ "generic-ohci";
|
||||||
|
+ reg = <0x05200400 0x100>;
|
||||||
|
+ interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
+ clocks = <&ccu CLK_BUS_OHCI1>,
|
||||||
|
+ <&ccu CLK_USB_OHCI1>;
|
||||||
|
+ resets = <&ccu RST_BUS_OHCI1>;
|
||||||
|
+ phys = <&usbphy 1>;
|
||||||
|
+ phy-names = "usb";
|
||||||
|
+ status = "disabled";
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ ehci2: usb@5310000 {
|
||||||
|
+ compatible = "allwinner,sun50i-h616-ehci",
|
||||||
|
+ "generic-ehci";
|
||||||
|
+ reg = <0x05310000 0x100>;
|
||||||
|
+ interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
+ clocks = <&ccu CLK_BUS_OHCI2>,
|
||||||
|
+ <&ccu CLK_BUS_EHCI2>,
|
||||||
|
+ <&ccu CLK_USB_OHCI2>;
|
||||||
|
+ resets = <&ccu RST_BUS_OHCI2>,
|
||||||
|
+ <&ccu RST_BUS_EHCI2>;
|
||||||
|
+ phys = <&usbphy 2>;
|
||||||
|
+ phy-names = "usb";
|
||||||
|
+ status = "disabled";
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ ohci2: usb@5310400 {
|
||||||
|
+ compatible = "allwinner,sun50i-h616-ohci",
|
||||||
|
+ "generic-ohci";
|
||||||
|
+ reg = <0x05310400 0x100>;
|
||||||
|
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
+ clocks = <&ccu CLK_BUS_OHCI2>,
|
||||||
|
+ <&ccu CLK_USB_OHCI2>;
|
||||||
|
+ resets = <&ccu RST_BUS_OHCI2>;
|
||||||
|
+ phys = <&usbphy 2>;
|
||||||
|
+ phy-names = "usb";
|
||||||
|
+ status = "disabled";
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ ehci3: usb@5311000 {
|
||||||
|
+ compatible = "allwinner,sun50i-h616-ehci",
|
||||||
|
+ "generic-ehci";
|
||||||
|
+ reg = <0x05311000 0x100>;
|
||||||
|
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
+ clocks = <&ccu CLK_BUS_OHCI3>,
|
||||||
|
+ <&ccu CLK_BUS_EHCI3>,
|
||||||
|
+ <&ccu CLK_USB_OHCI3>;
|
||||||
|
+ resets = <&ccu RST_BUS_OHCI3>,
|
||||||
|
+ <&ccu RST_BUS_EHCI3>;
|
||||||
|
+ phys = <&usbphy 3>;
|
||||||
|
+ phy-names = "usb";
|
||||||
|
+ status = "disabled";
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ ohci3: usb@5311400 {
|
||||||
|
+ compatible = "allwinner,sun50i-h616-ohci",
|
||||||
|
+ "generic-ohci";
|
||||||
|
+ reg = <0x05311400 0x100>;
|
||||||
|
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
+ clocks = <&ccu CLK_BUS_OHCI3>,
|
||||||
|
+ <&ccu CLK_USB_OHCI3>;
|
||||||
|
+ resets = <&ccu RST_BUS_OHCI3>;
|
||||||
|
+ phys = <&usbphy 3>;
|
||||||
|
+ phy-names = "usb";
|
||||||
|
+ status = "disabled";
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
rtc: rtc@7000000 {
|
||||||
|
compatible = "allwinner,sun50i-h616-rtc";
|
||||||
|
reg = <0x07000000 0x400>;
|
||||||
|
--
|
||||||
|
2.20.1
|
||||||
|
|
||||||
@ -0,0 +1,84 @@
|
|||||||
|
From 1bc12a9ae690a22a525f9b71778022bb4533fec1 Mon Sep 17 00:00:00 2001
|
||||||
|
From: Andre Przywara <andre.przywara@arm.com>
|
||||||
|
Date: Wed, 16 Jun 2021 18:32:36 +0100
|
||||||
|
Subject: [PATCH 5005/5006] arm64: dts: allwinner: h616: OrangePi Zero 2: Add
|
||||||
|
USB nodes
|
||||||
|
|
||||||
|
The OrangePi Zero 2 has one USB-A host port, VBUS is provided by
|
||||||
|
a GPIO controlled regulator.
|
||||||
|
The USB-C port is meant to power the board, but is also connected to
|
||||||
|
the USB 0 port, which we configure as an MUSB peripheral.
|
||||||
|
|
||||||
|
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
|
||||||
|
---
|
||||||
|
.../allwinner/sun50i-h616-orangepi-zero2.dts | 41 +++++++++++++++++++
|
||||||
|
1 file changed, 41 insertions(+)
|
||||||
|
|
||||||
|
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts
|
||||||
|
index 02893f3ac99d..cb8600d0ea1e 100644
|
||||||
|
--- a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts
|
||||||
|
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts
|
||||||
|
@@ -49,8 +49,24 @@
|
||||||
|
regulator-max-microvolt = <5000000>;
|
||||||
|
regulator-always-on;
|
||||||
|
};
|
||||||
|
+
|
||||||
|
+ reg_usb1_vbus: regulator-usb1-vbus {
|
||||||
|
+ compatible = "regulator-fixed";
|
||||||
|
+ regulator-name = "usb1-vbus";
|
||||||
|
+ regulator-min-microvolt = <5000000>;
|
||||||
|
+ regulator-max-microvolt = <5000000>;
|
||||||
|
+ vin-supply = <®_vcc5v>;
|
||||||
|
+ enable-active-high;
|
||||||
|
+ gpio = <&pio 2 16 GPIO_ACTIVE_HIGH>; /* PC16 */
|
||||||
|
+ };
|
||||||
|
};
|
||||||
|
|
||||||
|
+&ehci1 {
|
||||||
|
+ status = "okay";
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
+/* USB 2 & 3 are on headers only. */
|
||||||
|
+
|
||||||
|
&emac0 {
|
||||||
|
pinctrl-names = "default";
|
||||||
|
pinctrl-0 = <&ext_rgmii_pins>;
|
||||||
|
@@ -76,6 +92,10 @@
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
+&ohci1 {
|
||||||
|
+ status = "okay";
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
&r_rsb {
|
||||||
|
status = "okay";
|
||||||
|
|
||||||
|
@@ -211,3 +231,24 @@
|
||||||
|
pinctrl-0 = <&uart0_ph_pins>;
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
+
|
||||||
|
+&usbotg {
|
||||||
|
+ /*
|
||||||
|
+ * PHY0 pins are connected to a USB-C socket, but a role switch
|
||||||
|
+ * is not implemented: both CC pins are pulled to GND.
|
||||||
|
+ * The VBUS pins power the device, so a fixed peripheral mode
|
||||||
|
+ * is the best choice.
|
||||||
|
+ * The board can be powered via GPIOs, in this case port0 *can*
|
||||||
|
+ * act as a host (with a cable/adapter ignoring CC), as VBUS is
|
||||||
|
+ * then provided by the GPIOs. Any user of this setup would
|
||||||
|
+ * need to adjust the DT accordingly: dr_mode set to "host",
|
||||||
|
+ * enabling OHCI0 and EHCI0.
|
||||||
|
+ */
|
||||||
|
+ dr_mode = "peripheral";
|
||||||
|
+ status = "okay";
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
+&usbphy {
|
||||||
|
+ usb1_vbus-supply = <®_usb1_vbus>;
|
||||||
|
+ status = "okay";
|
||||||
|
+};
|
||||||
|
--
|
||||||
|
2.20.1
|
||||||
|
|
||||||
Loading…
x
Reference in New Issue
Block a user